Tool/software:
Dear Texas Instruments,
we use ADCS7476 in a new product. I develop firmware module for this converter.
From Q&A "ADCS7476: Datasheet specs regarding t8 (SCLK FE to SDATA high impedance)"
Q: (Angela Peters) "For VDD = 5V, t4 (Data access time after SCLK falling edge (FE)) is 20 ns max and t8 (SCLK FE to SDATA high
impedance) is 25 ns max. Does this mean on the 16 SCLK FE, I may have only 5 ns to read the last bit out?
A: (Abhijeet Godbole) "After 16th clock FE you have MINIMUM of 5ns to read the LSB before SDO goes tri state."
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The word MINIMUM here is confusing
Does the answer imply "you have MAXIMUM of 5ns to read the LSB before SDO goes tri state." , or to re-phrase it
"you have ONLY 5ns to read the LSB before SDO goes tri state." ?
My question is about VDD=3.3V for which T4 = up to 40ns and T8 = up to 25ns. Following from the answer above,
does it mean that the output may go tri-state BEFORE even the last data bit can be available for readout ?
Please explain the meaning of T4 data access time which is greyed out in timing diagram in Figure 2.
Is it latency from the negative edge of clock signal applied to the SCLK pin to the valid data on the SDATA pin ?
Many thanks in advance for bringing clarity to your data sheet SNAS192G –APRIL 2003–REVISED MAY 2016 !
