I am creating a bus functional model in VHDL to test VHDL source code that interfaces with an ADCS7476. For VDD = 5V, t4 (Data access time after SCLK falling edge (FE)) is 20 ns max and t8 (SCLK FE to SDATA high impedance) is 25 ns max. Does this mean on the 16 SCLK FE, I may have only 5 ns to read the last bit out?
-
Ask a related question
What is a related question?A related question is a question created from another question. When the related question is created, it will be automatically linked to the original question.
