ADS8681: Consequtive multiple register read access

Oba

Part Number: ADS8681

Tool/software:

Hello,

My customer has a question for ADS8681,

When the converted data is required, CS signal must be high during t_conv_max period.

But if conversion data is not needed and executing multiple consequtive register read access like the below figure, does CS signal have to be high during t_conv_max?
Is shorter CS HIGH period less than t_conv_max acceptable? If acceptable, what is the minimum CS high time?

Regards,
Oba

5 months ago

0 Tom Hendrick 5 months ago

TI__Guru**** 181521 points

Hi Obata-san,

Please keep the full 'wait for tCONV_MAX' even when reading register data. The pins is CONVST/CS, so there is no way to break that 'dual functionality', even if you are reading register data, there is still a conversion going on inside the ADS8681 device.

0 Oba 5 months ago in reply to Tom Hendrick

TI__Genius 17515 points

Hello Tom,

Thanks for your reply.
In this case, they don't need ADC conversion data during the register read.
But could anything bad behaviour happen?

Regards,
Oba

0 Tom Hendrick 5 months ago in reply to Oba

TI__Guru**** 181521 points

Hi Obata-san,

There is no data available on the consequences of short cycling the CONVST/CS timing. Having two different 'read' routines is just going to add complexity to the software for minimal time savings so I don't see any benefit to the customer.

0 Oba 4 months ago in reply to Tom Hendrick

TI__Genius 17515 points

Hello Tom,

The customer says that ignoring CONVS/CS timing for the consequtive read can reduce the access time.
I don't know why they want to reduce such a small time as you said, but they says it has a benefit.
Is it acceptable?

Regards,
Oba

+1 Tom Hendrick 4 months ago in reply to Oba

TI__Guru**** 181521 points

It is not recomended to reduce the CONVST/CS timing.

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ADS8681: Consequtive multiple register read access