Tool/software:
Hi,
The first sample after an ADC reset seems to always result in a modulator saturation (MOD_FLAG bit of the STATUS register). All other samples are fine. What can be the cause of this?
BR
/F
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Tool/software:
Hi,
The first sample after an ADC reset seems to always result in a modulator saturation (MOD_FLAG bit of the STATUS register). All other samples are fine. What can be the cause of this?
BR
/F
Hello Fredda,
I checked the first conversion result after reset on an EVM and the MOD_FLAG bit is not set, which is the expected correct operation.
The only other possible explanation is that the ADC input voltage has exceeded the full-scale input by 10% or more. This could occur if an input amplifier output went all the way to supply rail (5V), as an example. The EVM uses a 2.5V reference; forcing the input to 5V (this is within the absolute input voltage range of the ADC but exceeds the full scale 2.5V by 100%) results in the MOD_FLAG getting set.
I would check the ADC inputs with a scope during reset to see if there are any voltage glitches.
Regards,
Keith
I have the input configured as:
This will give:
and:
So in theory the input voltage will never exceed the full-scale input by more than 8%.
Range is set to 1x and the precharge buffers in the ADC are active and thus the absolute input voltage of VAINP and VAINN is limited to:
However, that may not have an impact on the situation.
Just started investigating this so I will definitely check with a scope.
Thanks.
/F
Hello Fredda,
You are right at the edge of saturation if the TIA goes to the 5.2V rail. Also, if the reference is not low impedance, there may be a settling time error of the reference due to a load change on the REFP pin immediately after reset. I would also check the reference with a scope during reset.
Regards,
Keith