Tool/software:
I'm interfacing the AFE with a Xilinx eval board. I'm using the AFE58JD18EVM with LVDS 1X clk rate with the 16X serial data rate. I'm using the data in Lsb first mode and I successfully recover the frame clock X"FF00" and have used a number of different test patterns out of the AFE but they don't always show up in the same place. For a particular pattern they do but depending on the pattern it does not. There is no timing diagram for the 16x serial data rate but I would assume that in Lsb first mode I'd receive bit o would arrive with the first '1' of the recovered frame clk and bit 15 would arrive with the last '0' of the frame clk.
