Tool/software:
Hi Team,
I am using the adc12dj5200's ddc mode，the adc's clock is 5.2GHz.I use jmode16 to reduce the sampling rate to 650MSPS.In FPGA,The jesd204b's configuration as shown in the following figure.And the jesd204b's core clk is 81.25MHz,the Sysref clk is 5.078125MHz.
And the adc's registers list as shown in the following figure.
24'h0000B0, //soft_reset,self clearing for 750ns last
24'h002B15, //all time default
24'h02A230, //all time set
24'h02C200, //all alarm will not be masked
24'h020000, //JESD_EN = 0
24'h006100, //CAL_EN = 0
24'h0220CA, //FREQA0
24'h022139,
24'h0222D9,
24'h022349,
24'h020110, //JMODE = 16
24'h02020F, //K=16
24'h020500, //test_mode,0:normal
24'h006001, //all time default
24'h021500, //select which of 4 nco used to as active nco.[3:2] CSELB & [1:0] CSELA. range:0-3 00:use nco0 for chA and chB
24'h020400, //8b/10b offset_binary use_syncse_pin:all time default
24'h002920, //set sysref_recv_en =1
24'h002960, //set sysref_proc_en = 1 & sysref_recv_en = 1
24'h002970, //set sysref_proc_en = 1 & sysref_recv_en = 1 & zoom in sysref window status,smaller delay
24'h002969, //set sysref_delay according to sysref_pos
24'h006101, //CAL_EN = 1
24'h020001, //JESD_EN = 1
24'h006C00, //CAL_SOFT_TRIG = 0
24'h02C100, //alarm flag,if =1.alarm active
24'h006C01, //CAL_SOFT_TRIG = 1 ;form 0 to 1 means a cal_trig generated,start calibration.
delay 100usec
24'h021902,
24'h021903
According to the above configuration, the nco frequency is about 1.5GHz,my jesd204b link cannot be stably established, and the SYNC signal will frequently jump.But strangely, if I don't configure the FREQA0 register and keep its default value of 0xc000000, the link can still be established normally and stably.
I don't know how to solve this problem, can you help me?
Look forward to your reply！
