AMC7836: Observed spike on DAC output

Hi Zan,

I don't believe this is normal. The datasheet shows a different power-off sequence plots and how the DAC behaves, but none show a reset command. If you do the reset without powering off the supplies, do you still get this glitch? And the opposite, if you just power off the device without a reset do you see the glitch?

Thanks,
Erin

Hi Erin,

to amend the description from Zan - this is the behavior at the power-off of the module that includes AMC7836 component. All the power supply rails go down with a bit different decay times and reset goes to 0 because uC looses power supply. Looks like the AMC7836 power down sequence is uncontrolled. We found that the positive voltage spike during power-off happen on different DAC outputs and not on all parts. Please note that all the DAC outputs are configured for negative voltage supply, so this positive spike is very problematic.

You mentioned that there are power-off sequence plots in the datasheet - can you please point to them?

Robi

Above is the plot showing DAC transient when RESET was pulled down and power supplies were on.

Green is the +3.3V power supply (IOVDD pin on AMC7836IPAP).

Purple is the inverted RESET signal (Pin 2 on AMC7836IPAP)

Magenta  is -5V (AVEE pin on AMC7836IPAP)

Yellow is the DAC 9 output AMC7836IPAP)

Above is the requested plot where ~RESET pin was tied to +3.3V supply and our board was powered down.

Hi Samo,

For reference, the shutdown plots are figures 32 to 35. These plots are more for a sudden shutdown of specific power supplies, but in all cases the DAC outputs should follow AVEE. Just to confirm, are all of your AVSS supplies tied to AVEE?

To follow up on your comments, can you give more detail about "different DAC outputs and not on all parts"? Are there specific DACs that have this issue? Have you tried performing an a-b-a swap where you swap a bad and good device between the two boards and see if the issue follows the DACs?

Thanks,
Erin

Hi Erin!

Thanks for your replies. Below is the schematic of the AMC7836IPA that we use.

Some more details of the use case:

1. We use DAC outputs 0 to 13 (DAC0 to DAC13) to feed gates of GaAs HEMTs. 

2. We only use negative range (-5V to 0V)

3. We can't supply positive voltage to GaAs HEMTs above +0.2V as this forward biases the gate and this causes degradation of GaAs HEMT. The positive spikes in images above show that spike goes to +0.7V. This is because the gate-source junction of the GaAs HEMT  starts clamping the TI DAC output.

4. We noticed that some of our boards do not exhibit spikes on TI DAC. We noticed that some boards do exhibit spikes. Hard to say what is the percentage of boards that are affected.

5. We noticed that positive spikes appear differently across affected boards. We know that on one board DAC9 and DAC13 are affected. On second board only DAC 14 is affected. On third board DAC6, DAC9 and DAC13 are affected. We are testing more boards and we'll update on the results.

6. We haven't tried to replace two chips between operational and affected board yet.

7. We tried to disconnect the GaAs HEMT and checked affected unconnected DAC9. The spike still exists - that means it comes from the DAC.

8. We noticed that temperature plays a role. Spikes at cold are much larger. We will share plots soon.

Questions:

1. Figures 119 and 120 in the datasheet show transient responses when DAC is sourcing capacitive loads. GaAs FETs have high impedance (not sure if capacitive). Could that be the cause? If yes why not all the DACs behave the same?

2. We noticed we can suppress spikes by adding 220uF on pin 49 (REF CMP). Datasheet requires 4.7uF. Can you f9ind out if we can increase this capacitance to 220uF? What are we doing with that?

2. We ad

Hi Samo,

Appreciate the detailed information! Looks like there isn't an exact DAC correlation. I'm going to try this on an EVM when work resumes next week, I wonder if there's some sort of shut-down sequencing required to avoid these types of spikes. I'm not sure why adding more capacitance to the reference would remove the spike, that's also something I'll take a look at. 

Can you see if adding a small capacitor on the DAC outputs to see if this prevents the spike?

Thanks,
Erin

As promised spikes do change with temperature:

Thot (+85degC):

Tcold (same board same DAC output as above):

Hi Erin!

We need your help on understanding if we can add 220uF on REF_CMP pin?

As said before spikes are under control on one board if we add 220uF. See images below:

Troom:

Tcold:

The spike shows itself but it is still below 0V which is OK for us. 

We need to try on more boards. But please explain if this is safe!

Hi Erin!

One more question on AMC7836IPAP chip. This is not related to the spike above but it is for our general understanding:

We noticed that AVssth level, which is crucial for DAC auto-ranging, can have levels between -3.5V and -1.5V.

Does this cover chip to chip variation?

Or is this intended as hystheresis?

For example if we apply -3V to the AVss pins (and +5V to AVCC) what would be the result of autoranging?

Will DAC output be set from 0V to -3V for all chips?

Will DAC output depend on chip to chip: on some from 0V to -3V and for some 0V to +5V.

Your answers are very appreciated,

BR Samo

Hi Samo,

How cold are you going when testing the glitch? I assume the original issues were found at room temperature?

I don't foresee a significant issue with loading the reference with the 220uF capacitor. Do note that with this extra load, the reference will take longer to get to the ideal 2.5V. 

About the general info:

The threshold is for chip-to-chip variation, yes. In general, it's expected that your highest VSS voltage is -5V. This table in the datasheet shows this. If you were to use a -3V VSS, there's a chance the autodetection won't work as expected. It's likely chip dependent and applying at least -3.5V will guarantee all DAC outputs will be set to the negative range.

Thanks,
Erin

Hi Erin!

Yes, the problem was seen at room temperature.

Have you been able to reproduce the spikes on the EVM?

Do you have any other advice how to suppress the spike?

Would it be possible to have a meeting to discuss this issue and potential solutions?

We need a solution for this urgently and preferably without layout change.

BR Samo

Hi Samo,

I wasn't able to reproduce the issue on the EVM, but I'm not too surprised by this seeing that the DACs affected are random. So, a 200uF cap on the REF_CMP pin won't cause any issues for your DAC output, but may cause issues on the ADC side.

Out of curiosity, have you tried implementing a shutdown sequence, where you either turn off the DACs or performing a reset before turning the supplies off? 

Thanks,
Erin

Hi Erin!

Our case is the power supply removal. We can't implement shutdown sequence as we immediately loose microcontroller.

What we tested are these configurations: 

1. We tied ~RESET to Power supply and powered off the thing. In this case reset stayed up longer but it did not help.

2. We kept all power supplies on and only switched ~RESET to zero from a uC. This works fine but it is not our case.

Hi Samo,

In this case I mean either doing the reset or shutting off the DACs before doing the power shutoff. To me at least, it looks like the DAC is being re-ranged during shutoff into the positive range, causing this spike. So I'm curious if either setting the DAC to zeroscale, turning off the DAC, or just full resetting the device may fix this, or at least lessen the spike. 

Thanks,
Erin

That's the point - It is a normal occurrence that our equipment experiences power outages.

We can't switch of DACs and keep power supplies runing for 30 - 50 ms.

And yes - it looks to me that DACs go into autoranging after negative supply goes above threshold. What's weird to me is how beacuse 3.3 digital voltage is already quite low (<1V). 

Hi Samo,

Would it be possible to probe both the DAC output and the VREF_CMP pin during the transient? The DAC output should be clamped to VSS during alarm or reset events, but in normal operation a negative glitch on the VREF would look like a positive glitch on the DAC (when in the negative range).  Do you have a capacitive load on the DACs as well? A larger load, like >100nF?

Hi Paul!

Below is the oscillogram of REF_CMP voltage and DAC output (Vg12_LNA).

From previous measurements you can see that reset goes down 5ms before the positive glitch on DAC.

To me VREF_CMP looks clean.

It is true that DAC output should get clamped to VSS during regular operation. What about the power cycle case where Vss is not defined?

As explained below this behaviour is random across DACs and across chips.

I still blame autoranging but I do not know internals of the chip. Can autoranging work when digital supply is down? Is it implemented in analog part?

We use capacitive load - more accurately check image below (the stuff in dotted rectangles is internal to ICs we use and we can't change):

Hi Samo,

Nir contacted me to set up a meeting, so hopefully we can resolve this soon.

A designer looked at the potential downsides of going the 220uF on REF-CMP route, and he said the only concern he saw would be a longer rising time on the internal reference. If your setup doesn't immediately need the DACs and ADC when power turns on, this shouldn't be an issue. I tested the rise time on bench (with a much smaller capacitance of 90uF, we don't have a 200uF on hand here) and did not see an issue. The ultimate way of solving this issue would be to implement some sort of sequencing, but that would involve a lot of rework for your board, so that's not ideal. 

Thanks,
Erin

Hi Samo,

I am not convinced this is an auto-range issue.  Even during auto-range, the DAC should start clamped to the negative supply until the supplies are valid and the channels can be enabled.  

In your initial post, you mention in comment #7 that you have isolated the DAC in some cases.  Can you share that scope image? Can you confirm on some other channels as well? Would you ever expect to see the GaAs PA sink current when there is a transient on the gate? For example, can you remove the VDRAIN from you PA? 

Hi Paul!

The power supplies are no longer valid at power outage. The Vssth for autorange (see Table above) is -3.5V to -1.5V. When Vss ramps down from -5V to Vssth the autorange could happen if that circuit is still capable of doing smth. I'm not saying I am 100% sure this is the root cause but it is far from disproven in my view.

Here are the plots of two DAC outputs on the same chip. Firstly with regualr load (33ohm + 1uF) and secondly with open load (33ohm removed).

Hi Samo,

I sent an email to Eran, but the designer would like to see if we could get one of your problem devices sent to us so we could dig further into this issue. He also recommends the shutdown sequence to be VSS - +5V- IOVDD, instead of the +5V first. We could also continue this thread in email if you feel that would be more beneficial.

Thanks,
Erin