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Original question:

ADS1263: ADS1263 conversion time issue when using more than one channel for voltage differential measurement

ADS131M08: Latency (reading vs reality).

William Pringlemeir
Prodigy 10 points
Part Number: ADS131M08

Tool/software:

The device is configured to continuous conversion mode for default 4kS/s.  I have a DAC output with some lower latency op-amp circuit which is feed to a channel of the ADC (ads131m08).  I use a cross-correlation and the latency seems to be the sample period.  Ie, about 250µs for the 4kS/s rate.  I guess the SINC filters uses multiple readings (OSR) during this period to complete a conversion which is then sent of SPI.  I am not concerned about start up conditions, but the 'latency' as per the current conversion (with significant history) against what would be read from a AIN pins.  I understand the reading are filtered (so an equivalent filter on the pins).

The DAC and two ADC channels are connected to analog control system.  The DAC/ADC1 is the input and ADC2 is a feed back channel on the control output.  I wish to observe the delay of the control system (and tracking). I read the Conversion latency in delta-sigma converters appnote (and have other ADCs where explicit conversion diagrams are given).  I did not find this for the ADS131M08, but I may have missed it in the data sheet?  According to the app note, conversion time and cycle latency might be keywords.  The ADS131 seems to only have details on startup and global chop modes (as far as I could see). 

Thanks for any help,

Bill Pringlemeir.

  • +1
    TI__Guru 52496 points

    Hi William Pringlemeir,

    The ADS131M08 startup behavior is shown in the image below (see section 8.4.2). This is equivalent to the "first conversion latency" in the app note you referenced. This latency applies at startup, when a RESET is triggered, or when you synchronize the ADC using the SYNC pin. Importantly, this specific device does not gate the unsettled conversion data specifically during synchronization, so you will still get DRDY transitions during the first two conversion periods even though this is unsettled data. All data during startup and RESET is settled

    After the first conversion latency is over, the data will be available at approximately 1 / data rate, which is the "second and subsequent latency" mentioned in the app note. Note that because the ADS131M08 is a simultaneous sampling ADC, all 8 channels sample at the same time and the "first conversion latency" occurs concurrently, not in series as would be the case for a multiplexed ADC

    -Bryan

  • 0 in reply to Bryan Lizon86
    Prodigy 10 points

    Thanks.  It is a different form.  `tDATA = 1/ fDATA` seems to be the implication from the data sheet and matches your answer... or one cycle latency (which includes conversion times).