Other Parts Discussed in Thread: TSW12QJ1600EVM
Tool/software:
Hi exparts,
As in the TSW12QJ1600EVM configuration, we are considering daisy chain using the PLLREFO +/- of the first-stage ADC as the second-stage clock. In this case, the performance of the second-stage ADC may change depending on the signal quality of PLLREFO+/-.
Q1. Are there any restrictions or conditions that allow the second-stage ADC to perform as well as the first-stage ADC?
Q2. Are there any data for:
PLLREFO+/- quality of the first-stage ADC
CLK+/- quality of the second-stage ADC acceptable (delay amount, jitter, etc.)
Regards,
Hiromu