Tool/software:
Hello, I am using ADS8688EVMA equipped with ADS8688. I have a question about running the SPI communication example connected to TMDISDK5749.
The ADS8688 data sheet explains as follows.
• Event 3: At the 16th falling edge of the SCLK signal, the device reads the LSB of the input word on the SDI line. The device does not read anything from the SDI line for the remaining data frame. On the same edge, the MSB of the conversion data is output on the SDO line and can be read by the host processor on the subsequent falling edge of the SCLK signal. For 16 bits of output data, the LSB can be read on the 32nd SCLK falling edge. The SDO outputs 0 on subsequent SCLK falling edges until the next conversion is initiated.
The SPI mode that I use is 1, with CPOL set to 0 and CPHA set to 1. This matches what is listed in the datasheet.
The SPI example was installed using TMDSIDK5749 rtos's pdk_am57xx_1_0_17, and tuning was performed, such as modifying the buffer to 32 bits to match the specifications of the chip performing ADC.
There is no problem sending data from the master to the slave. The SDI value changes at the rising edge of the clock, and the corresponding SDI value is maintained at the falling edge.
The problem lies in the process of sending data from the slave to the master (SDO). In SPI communication, if CPOL is 0 and CPHA is 1, the SDO value must change on the rising edge and remain unchanged on the falling edge. However, according to the ADS8688 data sheet, the MSB of the ADC result is output to SDO at the 16th falling edge. The master then reads the data at the 17th falling edge.
Upon verification with an oscilloscope, it was confirmed that the SDO value actually changes at the 16th falling edge.
The question is this: When the 17th (SCLK)clock's falling edge occurs and the SCLK signal changes to Low, the SDO's value is changed again by the slave, how can the master read the signal sent at the 16th clock's falling edge at the 17th clock's falling edge? There doesn't seem to be enough time.
