• State
  • Locked Locked
  • Replies 2 replies
  • Subscribers 47 subscribers
  • Views 85 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

ADC12QJ1600: Microchip Polarfire FPGA JESD204B configuration

ADC12DJ1600: JESD configuration

Mikael Krus
Prodigy 20 points
Part Number: ADC12DJ1600
Other Parts Discussed in Thread: ADC12QJ1600

Tool/software:

 (L) Hi,

I would like to configure the dual core ADC12DJ1600 in JMODE9, but only use the first core.

How should the FPGA IP be configured to support this? Especially with the lanes (L) parameter?

In a related thread I managed to get a quad device ADC12QJ1600 running with only the first core enabled in the FPGA IP by changing the lanes (L) parameter from 8 to 2.

From the datasheet for a dual device, lanes (L) parameter is specified as 3. Why is that? I would have expected it to be 4??

How should it be changed to cope with first core only running?

  • 0
    TI__Expert 6150 points

    Hi Mikael,

    The ADC supports a number of different Lane configurations for maximum user flexibility. If you look at tables 7-20 through 7-35 you can see exactly how the data is packed and which lanes the data arrives on. If you are only interested in a subset of the ADC cores then you can use this table to figure out which lanes you need to connect in your design and on the FPGA side limit the number of lanes.

    It will not be possible to use this trick for JMODE9 as the samples of the ADC are actually getting split across multiple lanes (see pic below) so you would not be able to just ignore some of the lanes and be able to re construct the data.

    If you can share your system requirements i can help make a recommendation for the jmode to use.

    Thanks,

    Eric

  • 0 in reply to Eric Kleckner
    Prodigy 20 points

    Hi Eric,

    Your plots show JMODE4.

    I was planning to use JMODE9, table 7-29 below which is 8-bit. Only input A of the ADC, so it looks like I only require 2 lanes.

    Can you please confirm?