Tool/software:
Hello, what is a correct clock mode in terms of clock polarity and phase? The timing diagram Figure 3 looks ambiguous : DOUT data is shown stable at the rising edge of clock pulse (so this is the perfect time for sampling) yet the text says the DIN is shifted inside the chip also at the rising edge of clock.
By definition the shifting of data must happen on both lines MISO and MOSI for both Master and Slave in sync and so is the sampling of data must be synchronized for both at the same time. But Figure 3 shows the stable times for shifting and sampling different for DOUT (MISO) and for DIN (MOSI) . This makes it difficult to find the synchronous clock edge for both to sample data.
The polarity of clock looks as been high in idle ('1') but the phase would be 2nd edge for DOUT (phase '1'), yet 1st for DIN (phase '0') ... cannot be like that
Please help.
