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THS1206: data_av line always keeping high

Varun Kumar
Prodigy 10 points
Part Number: THS1206

Tool/software:

I am trying to interface THS1206 with AMD artix 7 FPGA.
The ADC is configured for two channel in diffrential mode. When I am trying to run in Auto Scan mode by setting CR0 as  0c8h, the ADC data_av line is always keeping high.
The initialization process Followed are :

1)  write CR1 401h.

2) write CR1 400h

3.) write CR1 402h (for fifo reset).

4.) write CR0 0c8h,

5.) write CR1 410h.

where as for the same sequence if I am writing in step 4 as 020h or 028h (individual channels in diffrential mode) , the data_av line is toggling as required, and able to see output.

What wrong am  I doing here?
where as 

  • 0
    TI__Guru**** 180961 points

    Hi Varun,

    Welcome to our e2e forum!  The THS1206 is a pipe line converter and needs the CONV_CLK to toggle 7+TL times before DATA_AV goes active.  Once DATA_AV goes active, you can start reading the conversion results.  If you don't hold off on trying to read data, you can get into the case that you are describing here - DATA_AV does not toggle.  Can you provide a screen shot of your controls lines?

  • 0 in reply to Tom Hendrick
    Prodigy 10 points

    Hi Tom,
    Thanks for your reply.
    As per your request  have captured the control lines timings(attached here)

    I can see adc_dav (data_av) is high for 7 + TL (00 in my case).
    After that it goes low for half conv_clk, and output a single value (EE4) after that it remains high indefinitely.

    Where as for the same initialization sequence, when I write CR0 as 020h or 028h, I can see  adc_dav(data_av) line toggling and giving correct output(below snap shot for CR0 as 020h)

    Let me know if you need further inputs.

    Also, will it be possible for you to provide a sample FPGA interface driver code (either in VHDL or Verilog) to check with? 

  • 0 in reply to Varun Kumar
    TI__Guru**** 180961 points

    Hi Varun,

    Unfortunately I do not have any FPGA code to share.  Can you bring your /RD strobe half a clock cycle earlier (refer to Figure 30 in the datasheet)?  That should fix things.

  • 0 in reply to Tom Hendrick
    Prodigy 10 points

    Hi Tom,
    I did  brought /RD strobe half cycle earlier, still having the same issue, attaching scree grab

    do you suspect any HW connection issue. the HW is connected as below.

  • 0 in reply to Varun Kumar
    TI__Guru**** 180961 points

    Can you take a look at Figures 35, 36 and 37 and then using an o'scope see if you are getting a proper read and write signal?

  • 0 in reply to Tom Hendrick
    Prodigy 10 points

    Sure Tom, 
    I will have a closer look at these figures once again, 
    but I have only question, for the same timing condition, if CR0 is 020h or 028h, I am able to get the correct data.

  • 0 in reply to Varun Kumar
    TI__Guru**** 180961 points

    For each conversion cycle once the TL has been satisfied, you have to 'read' date to keep DATA_AV active.  You can try bringing in RD another quater cycle so that it is within the same conversion clock period.