ADC32RF55: JESD lane settings

Kei Kuwahara

Expert 8120 points

Part Number: ADC32RF55

Tool/software:

Hello team,

On the Table 7-32, JESD mode is L=8, M=2 for 12bit resolution.
However, my customer will only 1ch of this ADC.

Is it possible to set L=4, M=1 for 12bit resolution?
They want to save JESD lanes.

Best Regards,
Kei Kuwahara

4 months ago

+1 Chase W 4 months ago

TI__Mastermind 23860 points

Yes, use GUI tool to generate configuration for 8-2-8-20 bypass mode. Then use JESD page 0x28 to power down unused serdes lanes.

0 Kei Kuwahara 4 months ago in reply to Chase W

TI__Expert 8120 points

Hi Chase-san,

Thank you for your quick answer.

So in order to set the L = 4, should I set the 0x28 register to 0x0F? (00001111)

Also, how do I set the M = 1?

Best Regards,
Kei Kuwahara

+1 Chase W 4 months ago in reply to Kei Kuwahara

TI__Mastermind 23860 points

Hi Kei-san,

You do not have to set anything for M=1. The FPGA will only be looking at the one active channel and will inherently be M=1. That is correct for L=4 using the 4 lowest lanes (DOUT0-DOUT3).

Thanks

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ADC32RF55: JESD lane settings