• State Resolved
  • Locked Locked
  • Replies 5 replies
  • Answers 1 answer
  • Subscribers 45 subscribers
  • Views 144 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS131M02: Respond Frame Update Timing

Min Yoon
Prodigy 100 points
Part Number: ADS131M02

Tool/software:

Hello,

I would like to implement continuous SPI communication with the ADS131M02, independent of the DRDY pin, by sending a NULL command on every frame to read both the STATUS register and the ADC data. I plan to evaluate each frame’s STATUS register to decide whether to use its ADC sample. Before proceeding, I would like to clarify a few points and confirm that this approach is feasible:

  1. STATUS register sampling
    When exactly is the STATUS register value sampled for SPI transmission? If a command sent in frame N returns its response in frame N+1, is the STATUS register latched at the end of frame N, or does it continue updating up until the start of frame N+1?

  2. ADC FIFO behavior
    The ADS131M02 provides a two-sample FIFO per channel. If the FIFO is full when a new conversion completes, does the device overwrite the oldest sample (standard FIFO behavior), or discard the new sample and retain the existing contents?

  3. Continuous SPI vs. conversion timing
    If I initiate back-to-back SPI frames with only the minimum 5 µs inter-frame gap, regardless of DRDY pin, will this interfere with the ADC’s ongoing conversions or compromise data integrity?

  4. Data validity after idle periods
    For example, if there is a one-second gap between SPI frames, will the STATUS register and FIFO continue capturing conversions during that interval, so that the next read reflects samples up to that moment, or are they latched at the end of the previous frame?

Thanks in advance.

  • 0
    TI__Mastermind 45515 points

    Hi Min Yoon,

    See my answers below:

    1. The command is latched by the device at the end of the frame N.
    2. The data flow on this ADC is:  conversion data->output buffer->FIFO->DOUT pin, the content in the output buffer is updated with every new conversion data, but the content in the FIFO depends on how you read the data from the ADC. If you read the conversion data when it is available and do not miss reading any data, the content in the FIFO will be updated with the latest data, otherwise you may read the previous data and you may have to double read to get the latest data. Please notice that your MCU can only access the FIFO not the output buffer.
    3. 5us gap means you are sending more SPI frames during one ADC cycle (1/data rate). It really depends on what you send. Monitoring /DRDY to read data is strongly recommended. The transition from high to low on /DRDY indicates that the conversion data is ready for your MCU to read. You can use the falling edge of the /DRDY to trigger an interrupt on your MCU to read the data.
    4. If the data rate you set is higher than 1ksps, the conversion is still ongoing during one-second gap between your SPI frames and the STATUS register is constantly updated. For the content in the FIFO, see my answers in item #2 above.

    BR,

    Dale

  • 0 in reply to Dale Li
    Prodigy 100 points

    Hello Dale,

    Thank you for your answer. I would like to inquire about one more clarification, if that's okay.

    If I issue two SPI frames one second apart, the device latches the STATUS bits at the end of the first frame and then returns that same snapshot in the second frame. This means the Status data I received in the second frame reflects the status from one second earlier, even though the STATUS register itself updated during the 1-second gap. To read the current STATUS after 1 second, I would need to initiate a third SPI frame. Is this correct?


    Thanks,

    Min

  • 0 in reply to Min Yoon
    TI__Mastermind 45515 points

    Hi Min Yoon,

    When I said "the command is latched by the device at the end of the frame N", I meant the command like RREG, WREG command and son on.

    The STATUS register update does not depend on the command you send. For example, once new conversion data are available on CH0 and CH1 channels of ADS131M02 and the /DRDY is changed from high to low, the DRDY0 and DRDY1 bit in the STATUS register will be updated right away.

    BR,

    Dale

  • 0 in reply to Dale Li
    Prodigy 100 points

    Hello Dale,

    From what I understand, if I send either NULL cmd or RREG cmd for the STATUS register, the ADS131M02 will shift out a STATUS reg data. I also understand that the STATUS reg bits continues to update interanlly. 


    What I'd like to confirm is: If I initiate a SPI read Frame to receive the response for the previous frame - RREG cmd for STATUS Reg - is the STATUS reg data I received the most recent data until the CS is pulled low for the read Frame or is it the data snapshot from the end of last frame when the cmd was "latched"?

    Thanks,

    Min

  • +1 in reply to Min Yoon
    TI__Mastermind 45515 points

    Hi Min Yoon,

    The STATUS register data is the most recent/latest data until the first SCLK, not the /CS in your frame. When a frame starts, the SPI interface blocks the ADC data update including the DRDY status bits in the STATUS register. The first rising edge of SCLK starts the blocking. The ADC clock senses the blocking and synchronize the block to ADC module within the first 8 SCLK cycles. 

    For the FIFO behavior on ADS131M02, you can also check the section 8.5.4 ADC Output Buffer and FIFO Buffer in AMC131M02 datasheet.

    BR,

    Dale