ADC12QJ1600: Minimum sampling rate

Michael

Part Number: ADC12QJ1600
Other Parts Discussed in Thread: , ADC12QJ800

Tool/software:

Hello,

with the reference to this https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1290078/adc12qj800-adc12qj800?tisearch=e2e-sitesearch&keymatch=ADC12QJ800#, is the minimum sampling rate imposed by requirement on the minimum JESD rate (2.5Gbps) valid also for ADC12QJ1600?

In the ADC12QJ1600EVM SW, there cannot be set lower sampling frequency than 500MHz in the first planing tab. I guess this is the limitation of this SW only, right?

Michael

2 months ago

0 Rob Reeder 2 months ago

TI__Mastermind 38760 points

Hi Michael,

The min sampling rate of 500MSPS is set by the internal PLL loop BW of the device. This is specified within the ADC datasheet spec tables.

Regards,

Rob

0 Michael 2 months ago in reply to Rob Reeder

Prodigy 100 points

Ok, so with the PLL by-passed, we can use lower sampling rates down to the JESD minimum limit, right?

0 Rob Reeder 2 months ago in reply to Michael

TI__Mastermind 38760 points

Hi Michael,

Unfortunately, the min sampling rate is 500MHz, the PLL I am referring to is the internal PLL for the JESD.

Regards,

Rob

0 Michael 2 months ago in reply to Rob Reeder

Prodigy 100 points

So, this is different from ADC12QJ800 model or this answer (e2e.ti.com/.../adc12qj800-adc12qj800 is wrong?

+1 Rob Reeder 2 months ago in reply to Michael

TI__Mastermind 38760 points

Hi Michael,

Sorry that post is incorrect.

I will delete this in order to not create any confusion.

Thank you for bringing this to our attention.

Thx,

Rob

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ADC12QJ1600: Minimum sampling rate