Other Parts Discussed in Thread: CDCE62005,
Tool/software:
Hello,
I am new to the DAC world and trying to start my first design.
my system is built from an Avnet Microzed 7020 FPGA board, connected to a PCB with 2 DAC3484 and a CDCE62005.
My goal is to set a sine wave from one of the DAC's. I've got a DDS compiler in my FPGA that gives my a sine wave of 5MHz, and I manage to control the CDCE to output the right frequencies (I measured the DATACLK in the output side of the FPGA and it behaves as expected). I created a Vitis app that goes after the programming example of the datasheet, including a break to press the RESETB button, but for some reason, I keep getting DACCLK_gone and DATACLK_gone, and therefore output_gone, and alarm_from_pll and alarm_from_fifo.
the signals that I initialized are:
f_DACCLK=400MHz (at reference)
f_DACCLK_internal=800MHz
(P=5, N=8, M=16, PLL_ENA=1,PLL_SLEEP=0)
f_NCO= 10MHz (0x03333334)
f_DATACLK=100MHz (at output of FPGA, verified)
f_SYNC= 5MHz (derived from the equations of slaa584)
f_FRAME=25MHz (although it is not needed for the PLL circuit, this is the frequency I've set it to).
These are the initialization values of my DAC registers, transfered through a 3-wire SPI modue in the FPGA.
#define DAC_DEFAULT_CONFIG0 0x029C //allow inverse sinc for channel AB. interpolation=4, FIFO enabled
#define DAC_DEFAULT_CONFIG1 0x010E // parity disabled
#define DAC_DEFAULT_CONFIG2 0xF052 // define input as 16 bit data, enable mixer, enable nco, input as 2's comp
#define DAC_DEFAULT_CONFIG3 0xA000
#define DAC_DEFAULT_CONFIG7 0xD8FF
#define DAC_DEFAULT_CONFIG24 0x0c68 //single charge pump, prescaler=5, pll_ena=1
#define DAC_DEFAULT_CONFIG25 0x1074 //pll_m=16, pll_n= 8, vcoitune to 01 for normal pll operation
#define DAC_DEFAULT_CONFIG26 0xFC00 //pll_vco=63 (4GHz) pll_sleep=0
#define DAC_DEFAULT_CONFIG27 0x0800 //fuse_sleep=1
#define DAC_DEFAULT_CONFIG30 0x4444 //syncsel_qmc as SYNC
#define DAC_DEFAULT_CONFIG31 0x4440 //syncsel_dataformatter, syncsel_nco is SYNC
#define DAC_DEFAULT_CONFIG32 0x1101 //syncsel_fifoin syncsel_fifoout clkdiv_sync_sel source is SYNC (controlled by FPGA clocking wizard)
Ive checked my schema and it does not seem to have any problems, except for a floating ground in banks 34 and 35 of the FPGA (which I know I get got outputs from).
Please enlighten me I you think what could be the problem.
