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ADS1115: An offset occurs

cafain
Mastermind 6755 points
Part Number: ADS1115

Tool/software:

HI, Staff

An offset occurs

We are testing an analog input interface with 0-10V input using the ADS1115.
An offset occurs in the AD conversion result.
This effect tends to be particularly pronounced when C of a CR low-pass filter is connected.
For example, when AIN0=0V, the AD conversion result is about 1.9mV.

The circuit configuration is that the 0 to 10V input signal is resistively divided to 0 to 3V, then connected to a CR filter (C: 4.7nF, R: 499Ω) and then input to AIN0 of the AD converter.
The CR filter is based on the EVM circuit. Single-ended ±4096mV, data rate is set to 860SPS.

What causes the offset?
Please let me know.

regards
cafain

  • 0
    TI__Genius 14880 points

    Hi Cafain,

    Can you specify if you are using single-ended inputs or differential? What input range is the device set to? What is the measured voltage at AIN0? When you say it is 0V, is the input directly shorted to ground?

    Generally speaking, offset error in the ADC and PGA are due to transistor or resistor mismatches.

    Regards,
    Joel 

  • 0
    TI__Genius 14880 points

    Hi Cafain,

    Sorry, I see you mentioned single-ended inputs and +/-4.096V input range. Can you also share the resistor values of the voltage divider? If they are too large, they can cause a settling error, which might be the "offset" you are seeing. You might also try lowering the sampling rate, and checking to see if the issue improves. If it does, then it is likely a settling error.

    Regards,
    Joel

  • 0 in reply to Joel Meraz
    Mastermind 6755 points

    HI, Joel san

    Thank you for your help.

    The resistance values ​​of the resistor divider are 77kΩ/33kΩ.

    What does the settling error mean?

    regards,

    cafain

  • 0 in reply to cafain
    TI__Genius 14880 points

    Hi Cafain,

    Settling error refers to the fact that the resistance and capacitance seen at the input of an ADC form an RC time constant. This makes it so that, given an input step signal, the voltage at the filter capacitor or ADC sampling capacitor will rise to the input voltage over time (step response of an RC circuit). If sufficient time is not allowed for the voltage across the capacitor to reach the input voltage, within 1/2 LSB of the ADC input range, that is considered a settling error.

    Therefore, a high input resistance, such as a voltage divider, or high input capacitance will prolong the settling time of the voltage read by the ADC.

    Generally, higher sampling rates provide less time for the voltage at the input of the ADC to settle. Lower sampling rates provide more time, which is why I recommend lowering the sampling rate. If the error decreases, this would point to there being a settling error.

    What is the nature of the signal? Is it a time-variant signal, like a sinusoid, or a steady/slow-changing signal like a DC voltage or temperature reading?

    Regards,
    Joel