DAC38J84: clock input standard

lavanya bhatta

Prodigy 30 points

Part Number: DAC38J84

Tool/software:

Please let me know what is effect on DAC38J84 device performance if the input clock signal LVDS instead of LVPECL

2 months ago

0 Kang Hsia 2 months ago

TI__Guru* 78624 points

Hello,

If you use LVDS signal for the DAC38J84, the slew rate of the LVDS signal and also the inherent noise performance may create additional noise due to jitter. This may impact the overall phase noise of the DAC. Please see below two app notes for reference. Thank you!

https://www.ti.com/lit/an/slaa566/slaa566.pdf

https://www.ti.com/lit/an/slaa565a/slaa565a.pdf

0 lavanya bhatta 2 months ago

Prodigy 30 points

Hello Kang Hsia,

We are using an RF transformer (Part Number: TC1-1-13MG2+) to convert differential signals for DACCLKP & DACCLKN and the FPGA clock.

Currently, we are observing the NCO signal, but when using JESD, the DAC output is not coming.

Could you please help clarify the issue or provide guidance on possible causes?

0 lavanya bhatta 2 months ago

Prodigy 30 points

Hello Kang Hsia,

we are using RF transformer for converting differential signal (Part number:TC1-1-13MG2+) for DACCLKP & DACCLKN and FPGA Clock we are getting NCO signal only when we are using JESD DAC output not coming please clarify

0 Kang Hsia 2 months ago in reply to lavanya bhatta

TI__Guru* 78624 points

on the datasheet there are recommended clock interface, please follow the instructions and also refer to your clock driver instructions

lavanya bhatta said:
Currently, we are observing the NCO signal, but when using JESD, the DAC output is not coming.

I am not clear on your questions. There are various posts on JESD debug, you can refer to them as a starting point.

Data converters

Data converters forum

DAC38J84: clock input standard