TSW14J58EVM: I/O setting for G12, G13, H31, H32 pin (XCKU5P FPGA)

Hiromu Susami

Part Number: TSW14J58EVM
Other Parts Discussed in Thread: TSW12QJ1600EVM, , ADC12QJ1600, THS4541

Tool/software:

Hi exparts,

The TSW12QJ1600EVM data sheet provides instructions for using TSW14J58EVM.
The SYSREF +/- of the two ADCs of the TSW12QJ1600EVM are connected to the FMC connector each. (G12, 13, H31, 32 pins)

The pins (G12, 13, H31, 32) on the TSW14J58EVM side are directly connected to the FPGA (XCKU5P).

Could your tell me the I/O settings of this?

Regards,
Hiromu

1 month ago

0 Hiromu Susami 1 month ago

TI__Prodigy 640 points

Hi team,

Could you support this?

Hiromu

0 Eric Kleckner 1 month ago in reply to Hiromu Susami

TI__Expert 6150 points

Hello Hiromu,

You can check the ADCs datasheet for the VCM and Vdiff pp of the sysref input to the ADC and then match it on the FPGA side.

Thanks,

Eric

0 Hiromu Susami 1 month ago in reply to Eric Kleckner

TI__Prodigy 640 points

Hi Eric,

If we see the datasheet of FPGA(XCKU5P), it seems that LVPECL output isn't supported.
How TSW14J58EVM input right diff signal (for example, VID: >0.4V) to ADC12QJ1600 sysref input without external buffer?

https://docs.amd.com/viewer/book-attachment/PukeDYQrenc5OUQpPyCC3A/fQq1e3qru~eHvPovjuU79g-PukeDYQrenc5OUQpPyCC3A

Regards,
Hiromu

0 Rob Reeder 1 month ago in reply to Hiromu Susami

TI__Mastermind 37740 points

Hi Hiromu,

You can use an external voltage divider to knock the voltage down in order to make this interface to work.

Regards,

Rob

0 Hiromu Susami 1 month ago in reply to Rob Reeder

TI__Prodigy 640 points

Hi Rob,

Q1. Do we need FDA(THS4541) for this time? If we choose SUB_LVDS output, V_OCM should drop (0.9V =>0.3V) but V_OD should increase (0.15V => 1V).
Q2. To begin with, TSW12QJ1600EVM+TSW14J58EVM doesn't even inculde voltage divider or FDA. Why is it operating properly? That seems quite odd to me.

Regards,
Hiromu

0 Rob Reeder 1 month ago in reply to Hiromu Susami

TI__Mastermind 37740 points

Hi Hiromu,

Q1: No, this is not needed.

Q2: If this is working, then the voltage levels are compliant with each other. I would just check to make sure they are not above the abs max of the FPGA.

Regards,

Rob

0 Hiromu Susami 1 month ago in reply to Rob Reeder

TI__Prodigy 640 points

Hi Rob,

Rob Reeder said:
I would just check to make sure they are not above the abs max of the FPGA.

Thank you. Let me know any update.

Following e2e thread shows LVPECL interface should be used for CLK± of ADC12QJ1600. But as shown in XCKU5P datasheet, the FPGA output only supports 0.270Vpp (max, MIPI_DPHY_DCI_HS). This is lower than ADC12QJ1600 min. CLK± specs(min. 0.4Vpp). That's why I am confused. Should I really use LVPECL or ?

https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1286907/adc12qj1600-sp-adc-clocking-techniques?tisearch=e2e-sitesearch&keymatch=ADC12QJ1600%252525E3%25252580%25252580LVDS

Are the following statements correct?:

The combination of TSW12QJ1600EVM and TSW14J58EVM does not meet the input specification for the CLK+/- pin. But it's working fine. However, even if it works normally, it is necessary to use the LVPECL interface in order to meet the ADC datasheet specifications when designing.

Regards,
Hiromu

+1 Rob Reeder 28 days ago in reply to Hiromu Susami

TI__Mastermind 37740 points

Closing this post. Answered via email.

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TSW14J58EVM: I/O setting for G12, G13, H31, H32 pin (XCKU5P FPGA)