Tool/software:
Hello Dear Sit/Madam,
Working on our own custom PCB with XILINX UltraScale+ FPGA connected to ADS52J65 chip we stuck dfinitely with trying receiving any data after FPGA PHY sederialisation IP.
What we achieved so far:
1. ADC is powered OK with all the necessary voltages (1,15V and 1,8V)
2. ADC is properly reset and fed with register values.
3. Deserialisation IP in FPGA receives proper JESD204 "CGS" phase K28.5 symbols (after 10b/8b decoding certainly)
4. JESD204 "ILAS" phase passes succesfuly with all the R, A, Q and C link configuration bytes.
5. JESD204 SYNC signal is HIGH and stable.
but after end of ILAS phase FPGA PHY data output is constantly ZERO, no matter we set default ADC data from analog
S/H part or set any ADC test pattern (ramp, all '1', 0xAA 0x55 toggle etc.). Demodulator part is disabled forcing direct
ADC/TEST data forwarding to ADC's JESD serialisation part according to datascheet. However on FPGA PHY output
we see Link layer test patterns e.g. Repeated transmission of a lane alignment sequence.
When we clear TRANSPORT_LAYER_TESTMODE_EN bit, after CGS and ILAS phase we should see either raw samples of
analog data choosen ADC Test Pattern depending on EST_PAT_MODES register setting but we get ZEROs after comlete
ILAS phase. FPGA JESD204 IP (following PHY IP) shows all status and synchrobization signals OK.
Help us overcome this strange behaviour please! Do we missed so crucial setup or register setting?
Thaank you in advane for all your cystomer support and Waiting for QUICK rely.
Best Regards
Wojciech Lesniak
