• State Resolved
  • Locked Locked
  • Replies 5 replies
  • Answers 2 answers
  • Subscribers 46 subscribers
  • Views 101 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DAC3171: Questions regarding the power consumption

Shunsuke Yamamoto
Expert 7651 points
Part Number: DAC3171

Tool/software:

Hi team,

I have several technical questions regarding the operation of DAC3171. Could you please kindly answer them?

1. How do users configure the power down mode?

2. No clock means users stop inputting the signals to DAC core Clock(DACCLKP/ DACCLKN)?

3. Are there any configurations which is lower power consumption listed in page 14 of the datasheet(MODE 1, MODE 2, MODE 3, MODE4)?

Best regards,

Shunsuke Yamamoto

  • 0
    TI__Expert 5410 points

    Hi Shunsuke-San,

    They put the DAC  into sleep mode and full word width (Configure Address 0x06 appropriately) and turn off the DACCLKP/N.  MODE 4 is the lowest power consumption.

    Regards,

    Geoff

  • 0 in reply to Geoff Roth
    TI__Expert 7651 points

    Hi Geoff,

    Thank you for the answers. I received several additional questions regarding DAC3171. Could you please kindly help me to answer them?

    1. What are sleepa bit and sleepb bit? Do users need to configure these bits to put the device into power-down mode?

    2. How long does it take to change from normal mode(MODE 1 and MODE 2) to power-down mode(MODE 4)?

    3. To configure power-down mode, do users need to set sleep pin low or high first and DACCLKP/N are off?

    Best regards,

    Shunsuke Yamamoto

  • 0 in reply to Shunsuke Yamamoto
    TI__Expert 5410 points

    Hi Shunsuke,

    1. For channels A and B of the multi-channel devices

    2. Since it is a SPI write, this was never characterized and we do not have the data on that.

    3. If it does not call out a specific sequence in the datasheet, then either is acceptable.

    Regards,

    Geoff

  • 0 in reply to Geoff Roth
    TI__Expert 7651 points

    Hi Geoff-san,

    Thank you for the answer.

    1.  Do users need to configure these bits to put the device into power-down mode?

    2. It means the time of changing the mode depends on SPI speed. Correct?

    3. The datasheet states DAC is in sleep mode in mode 4, so I think sleep pin should be low. What do you think?

    Best regards,

    Shunsuke Yamamoto

  • +1 in reply to Shunsuke Yamamoto
    TI__Expert 5410 points

    Hi Shunsuke-San,

    1. Correct

    2. Correct

    3. It doesn't say in the datasheet if the hardware pin is dominate over the registers, this would lead me to believe it is an OR function so if the pin is left floating, it will pull low due to the internal pulldown but the registers will put the device to sleep.  If the customer wants to make sure it is in sleep mode this pin can be pulled high as well.

    Regards,

    Geoff