Tool/software:
Hi,
The datasheet of ADC3562 shows the formula to calculate tPD as shown in below.
I think the formula should be
tPD = 3 + tCDCLK + TDCLK/2 (tCDCLK >= 2.5ns)
tPD = 3 + TDCLK + tCDCLK + TDCLK/2 (tCDCLK < 2.5ns)
TDCLK / 2 should be added here.
Is my understanding correct?
PLS refer the following timing chart to understand it.
If my understanding correct, could you revise the datasheet to correct the formulas?
Best Regards, Taki
Hi Fadi-san,
Thank you for your reply offline. I will continue this discussion on this thread.
We, my customer and I are still confusing, so that please let us confirm your answer.
Your point in your answer in above and in the mail is shown in below.
- The explanation about Tpd in datasheet specification is correct and Tpd shown in figure 7.1 in the datasheet is not correct.
- Tpd is defined as the portion of the full device latency that will not change across sample rates.
Based on your answer, I looked into the table to understand the definition of tPD and found a difference in two portions in the table.
1. According to the table, tPD is about the time from sampling clock falling edge to DCLKIN falling edge.
2. On the other hands, the definition of tPD is propagation delay : sampling clock falling edge to DCLK rising edge.
The end point of time period for tPD is around DCLKIN falling edge in case "1" in above and DCLK rising edge in case "2".
Which is correct, case "1" or "2" for tPD definition?
Where, "2" in above and Figure 7.1 is saying same things, so that I expect "1" is correct.
Best Regards, Taki
Taki-san,
For #1, t_CDCLK is just a delay between the input DCLKIN and sampling clock. This delay is not related to the device but it will be dependent on the customer setup. This is indicating that the t_pd will change based on the relationship of DLCKIN and CLK (it is recommended that DCLKIN and CLK should be sourced from a common reference so their phase relationship is not constantly changing). This has nothing to do with the definition of t_pd.
For #2, there is some nuance. In a single clock latency device, you can, in theory, measure the t_pd from the falling edge of the sampling clock to the rising of DCLK that indicates it is the sample you are interested in. Note, if the device latency is higher than 1 clock cycle then this will be the t_pd + number of clock cycles. Depending interface mode, the device latency will change:
Thanks!
Cheers,
Fadi
