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ADS1299: ID Readback and Conversion Rate Behavior

Conor
Guru 15240 points

Part Number: ADS1299

Tool/software:

Hi,

We are currently evaluating the ADS1299 and have encountered a couple of unexpected behaviors that we would appreciate your insight on:

  1. ID Readback Value
    When reading the ID register, we receive 0x20, whereas we expect 0x1E for the ADS1299 device. Could you please advise what might cause the device to return 0x20 instead of the expected value?

  2. Data Conversion Rate
    We are observing the output data rate to be approximately 2kSPS for 0x95, and 1kSPS for 0x96. Could you help us understand what could be causing this discrepancy?

For reference:

  • We have confirmed that register writes and readbacks are functioning correctly.

  • GPIO1–4 outputs match the configured GPIO register values, so we believe the SPI communication is operating properly.

We would greatly appreciate your assistance in understanding these issues.

Best regards,

Conor

  • 0
    TI__Guru 69446 points

    Hi Conor,

    Thank you for your post. 

    What is the AFE clock source, CLKSEL setting, and the complete register configuration? Have you taken care to follow the power-on reset guidelines? You can issue a reset pulse after the analog and digital supplies have ramped to ensure the device is initialized properly.

    Regards,

    Ryan

  • 0 in reply to Ryan Andrews
    Guru 15240 points

    Hi Ryan,

    Ryan Andrews said:
    What is the AFE clock source, CLKSEL setting, and the complete register configuration? Have you taken care to follow the power-on reset guidelines? You can issue a reset pulse after the analog and digital supplies have ramped to ensure the device is initialized properly.

    We are using the ADS1299 in a configuration where channels CH1–CH7 are expected to be sampled at 500SPS. However, we are observing several anomalies in the device's behavior, as detailed below.

    1. Observed Behavior

    1.1 ID Register Value

    Upon reading the ID register, we consistently receive 0x20, whereas we expect 0x1E for the ADS1299.

    1.2 Continuous Conversion Rate

    When configuring CONFIG1 with the following values:

    • 0x96 → Results in 1kSPS

    • 0x95 → Results in 2kSPS

    This is inconsistent with our expectation of 250SPS and 500SPS, respectively.
    Moreover, when setting CONFIG1 to 0x97, the device does not perform conversions.

    1.3 Number of Active Channels

    Only CH1–CH4 appear to be active.
    Bytes 16–27 on DOUT, which correspond to CH5–CH8, remain at logic low and show no changes, as confirmed by oscilloscope measurements.

    2. Setup and Configuration

    • CLKSEL and PDN pins are pulled up.

    • DAISY_IN and CLK pins are pulled down.

    2.1 No Register Write

    After powering up, we perform a hardware reset:

    • RESET pin: H → L (500 µs) → H

    • Wait 500 µs

    • Then assert START pin: L → H

    In this condition (with default settings), the DRDY pin toggles at a 1 ms period, indicating a 1kSPS rate.
    However, according to the default CONFIG1 = 0x96, we expect 250SPS instead.

    2.2 Register Read After Reset

    After issuing the reset, we read the following register values:

    • ID: 0x20

    • CONFIG1: 0x96

    • CONFIG2: 0xC0

    • CONFIG3: 0x60

    • CONFIG4: 0x00

    This suggests all values except for ID match default expectations, and SPI read appears to be working correctly.

    2.3 Register Write and GPIO Behavior

    We then wrote the following values to the device:

    • CONFIG1: 0x95

    • CONFIG2: 0xC0

    • CONFIG3: 0xE0

    • CONFIG4: 0x00

    • CH1–CH8: 0x55 (Test signal enabled)

    • GPIO: 0x50 (Configured as output; confirmed output pattern as LHLH on GPIO4–1)

    After writing, we confirmed correct register values via readback and verified GPIO output levels using an oscilloscope.
    We then issued START and RDATAC commands. Under this condition:

    • DRDY pin toggles at 2kSPS

    • DOUT outputs:

      • Bytes 1–3: Normal status data

      • Bytes 4–15: Changing data

      • Bytes 16–27: Remain low (no activity for CH5–CH8)

    We also set CONFIG1 = 0xB5 to enable internal clock output on the CLK pin.
    Measured frequency: 1.923 MHz, which is significantly outside the specified 2.048 MHz ±0.5% (at 25 °C).

    3. Supply Voltages (measured)

    • DVDD: 3.44 V

    • DGND: 0.00 V

    • AVDD: 2.49 V

    • AVSS: –2.50 V

    • AGND: 0.00 V

    Given the above observations, we are concerned about the root cause of the incorrect ID, unexpected data rate, and inactive upper channels (CH5–CH8).
    Please advise on any additional items we should check, or if there are known conditions that may cause this behavior.

    Best regards,
    Conor

  • 0 in reply to Conor
    TI__Guru 69446 points

    Hello Conor,

    Thank you for the detailed description. How many devices are exhibiting this behavior? Can you try another board?

    The result pulse following power-up looks correct. However, the recommendation is to wait 2^18*tCLK = 128ms or longer before issuing commands or using the device. Can you try extending the time delay between /RESET -> H and START -> H? 

    The Device ID = 0x20 indicates that the IC is not reading the internal OTP bits correctly, which is causing it to initialize in a 4-channel configuration. That would explain why the data for CH5-8 are stuck at 0x00. You can refer to this post: [FAQ] ADS129x: Why does the Device ID register show the incorrect number of channels? - Data converters forum - Data converters - TI E2E support forums

    Can you check the voltage of all VCAPx and VREFP pins with respect to AVSS?

    Regards,

    Ryan