Other Parts Discussed in Thread: ADC12QJ1600
Tool/software:
Hello all,
I have a question regarding the CH_EN (0x209) register's functionality in the ADC12QJ1600. We previously configured our ADC to work as a quad channel device in JMODE8. We are now looking to modify its SPI programming to have it function as a dual channel device (also in JMODE8).
Comparing the JESD parameters for the quad vs. dual channel modes, it seems that we should be able to use the same clock rates and JESD parameters (with the obvious exception of the L and M parameters). I have modified my JESD core and GT quad base IP in my FPGA accordingly, and it appears to function as expected...but only when I set the ADC's CH_EN register to 0x3. This setting supposedly enables all four channels, which should not be needed.
Meanwhile, when I write a 0x1 to CH_EN, I expect to enable the two channels I have connected, but encounter JESD errors during my programming. Probing the SERDES lanes with an ILA shows that when I set CH_EN to 0x1 (channels A and B enabled), only one of my SERDES lanes transmits data, with the other appearing to be disabled. The same occurs when I set CH_EN to 0x2 (channels C and D enabled). In contrast, when CH_EN is set to 0x3, I have the two SERDES lanes transmitting data as expected.
In the ADC12QJ1600's datasheet, it says that channels C and D must be enabled to enable dual channel mode, but I don't quite understand why. Am I misunderstanding the CH_EN register's functionality, or is this indicating that I have somehow gotten my ADC stuck in an intermediate state and need to revisit my signal connections and JESD programming?
Thank you in advance!
Regards,
Roger
