DAC8760: About DAC8760 Spec

TTD,

Here are some answers to your post:

1. Operating the DAC output in voltage mode is similar to an op amp output. In operation near rails, the DAC output has a hard time driving the output to near the rail voltage. In the data sheet on page 7, we specify this condition based on a headroom or footroom voltage, and we say that the output may not be driven to 0.5V within the AVDD or AVSS supply voltage. This is certainly a function of the load, but we still make 0.5V the specification. If you want to operate down to exactly 0V voltage output, you would need to use a negative supply on AVSS. 

For DAC current output, this really isn't a problem. In current output, device can output 0mA without any issues. 

2. The ESD rating is 1.5kV for HBM for this device. It is associated with any other devices on the board. I would note that ESD HBM testing is very specific about how this is tested for devices. This is a JEDEC standard testing so that everyone runs this test in exactly the same way and that the same total energy is delivered to the device. There is a very basic description on different versions of the test are done:

https://www.electronicdesign.com/technologies/power/article/21799383/whats-the-difference-between-hbm-cdm-and-mm-test

3. The accuracy specifications of the VOUT and IOUT DACs should not change using the internal reference versus the external reference. We specify the DAC with an external reference to separate out the error from the DAC and any error from the reference. I would note that any error from the reference itself is equivalent to an extra gain error. The internal or external reference error would be added to the TUE as part of the calculation.

4, 5. I haven't seen the characterization for the short circuit currents for VOUT, REFOUT, and DVDD. I'm not sure if there's much information about the distribution or the drift. I'll look into this and post back.

6. When the VOUT is disabled, it goes into a Hi-Z output state. The leakage current is basically 1nA or less (as shown in Figure 7-43 on page 20 of the data sheet.

7. The maximum load resistance will be based on the headroom (or compliance voltage) of the device operation. The compliance voltage over temperature is shown in Figure 7-70. However, we generally use 2V as the rule for compliance voltage. If the maximum output current is 24V and the AVDD supply is 12V, then you would want to use 10V as the maximum operation. The maximum load would be 10V/0.024A = 417mA.

8. When the device is in IOUT mode, the leakage current is very small. I would imagine that this is is less than 1nA similar to the VOUT Hi-Z state. I would note that we specify the typical output impedance is 50MΩ.

9. I don't think have any accuracy and temperature drift data for the internal 4.6V DVDD. I'll take a look and see if there's any information about that.

10. When the internal reference is used, the current going back into REFIN is added as a load to the device. The current consumption of the device increases by about 30uA.

Joseph Wu

TTD,

3. In the DAC8760 specifications, the TUE listing assumes that the reference is external and is perfectly accurate. Again, you can use a reference with lower error or calibrate out the reference error with a measurement. However, if the reference has some error, then the DAC output also has some error. If the reference is off by 0.01%, then the DAC output will be off by a the same 0.01%. Because of this, the reference error looks like a gain error. To combine the reference error with the TUE, you can just add them together. If the TUE is listed as ±0.07%, and the reference has an additional error of 0.01%, then the new TUE would be ±0.08%.

4, 5, and 9. There are very little details about the short-circuit current limit of the VOUT. In the datasheet we list the typical of 30mA. This is likely when the output is tied to ground. In the details that I found, the short-circuit current limit is higher when tied to AVDD, when AVDD=18V. This is typically 38mA, with a variance of about 4mA. I would probably use similar numbers with a short-circuit to ground.
For the internal reference, the short-circuit current limit shorted to ground was about 24mA with a variance of about 0.8mA.
For the DVDD, the output value was about 4.605V with a variance of about 0.011V. The short-circuit current limit was about 35mA with a variance of about 1.4mA.
For all these values above, I didn't find characterization data. I had only found a listing of these values used in a table reviewing some data. There isn't much else I can add to these values.

7. I'm sorry I had missed this original question. However, I'm not sure what you're asking about for the power-on reset. The data sheet describes this reset in detail on page 31-32. If the power supplies momentarily drop or brown out, then the device resets as long as the DVDD is below 0.8V for about 1ms. For the AVDD supply, this POR threshold is 1V and also takes about 1ms to reset.

Joseph Wu

TTD,

I did want to point out Figure 8-4 in the data sheet (page 32). From this figure, you need to reach the operation threshold to make sure you are finished with the POR. Here is the figure:

In this figure, you need to get the supply into the green area to make sure the device is operating after a POR. The lower bound would be 2.4V for the DVDD, and 8V for the AVDD. 

After the device comes out of POR, we don't list an amount of time required to set up the device. However, I would use 200us as a wait time after POR. This is the time used for the DAC8775, which is a similar device. This time is needed to allow for the trim registers to be loaded into operation.

Joseph Wu

ttd,

ttd said:

Q11

How long does it take for the RESET bit in the reset register to transition from 1 to 0 after setting 1?

I believe that various register settings will not be correctly reflected until after the reset is complete. For this reason, I plan to introduce a fixed wait period after inputting a 1 to the RESET bit.

When setting the reset bit in the register, the register will reset. When you read back the register the value will have been reset back to 0.

ttd said:

Q12

Regarding Data Sheet 8.3.10 “Frame Error Checking”:
Is it correct to understand that “When CRC mode is enabled on the first frame after power-up” refers specifically to “the first write to the DAC after power-up is a configuration register 0x57 and set CRCEN bit” and does not apply if do setting of reset register?

The intent of the question is to verify the presence or absence of a NOOP command.

Best Regards,

When you reset the device, the device is placed back in it's original default state. Because of this, when a reset is performed, the device goes back to not using the CRC. After a reset, you would need to restart the CRC mode just as restarting the part. I'm not sure why you bring up the NOOP, but it's not needed except to read back a register.

Joseph Wu

ttd,

ttd said:

There are very little details about the short-circuit current limit of the VOUT. In the datasheet we list the typical of 30mA.

This is likely when the output is tied to ground. 

→Is there any reason why there is no detailed information on the min and max values?
　The reason I want to know is that we would like to specify a current limit value in our product specifications, but we cannot specify it unless we know even roughly the variation.

You said:

Generally, we don't specify a min max on the current limit value. There's a large variation on this parameter that may depend on voltage and temperature.

ttd said:

After the device comes out of POR, we don't list an amount of time required to set up the device. However, I would use 200us as a wait time after POR. This is the time used for the DAC8775, which is a similar device. This time is needed to allow for the trim registers to be loaded into operation.

→To summarize, is the following interpretation correct?

　"The release voltage for the DAC8760 is unknown. For reference, the DAC8775 requires a minimum wait time of 200 μs from reset release to register access, so the DAC8760 also has a wait time of at least that long."

Yes that is correct.

ttd said:

9. I don't think have any accuracy and temperature drift data for the internal 4.6V DVDD. I'll take a look and see if there's any information about that.

For the DVDD, the output value was about 4.605V with a variance of about 0.011V. The short-circuit current limit was about 35mA with a variance of about 1.4mA.

→Thank you for the reference value for the internal DVDD. Is this corect understanding that the short-circuit current is the value when shorted to GND? Also, when you investigated the actual values ​​of multiple units, did you find that the average was 35 mA with a variation of 1.4 mA?

That is correct. However, when I said variance, I mean that the 1.4mA is a single σ of distribution.

Joseph Wu

ttd,

There is one other thing that I've noticed about the CRC in the DAC8760 that is unusual and I wanted to point it out. If the customer is using the CRC mode, they should be aware of this behavior. Normally, one would expect that a transmission with an error in the CRC code would be presumed as having an error in it, so the command or data would be ignored. However, for this device there are a few exceptions that are programmed into the Verilog. I ran some tests for this, and have a list of these exceptions. This was also checked against the Verilog code.

I was able to verify with design that this is what was designed. During communications, CRC operation doesn't always behave the way you might expect. Here are a list of the commands and their expected results.

For the following write commands, the CRC error condition blocks the execution

• 0x01 Write DAC Data register – CRC error does not execute command and sets ALARM
• 0x55 Write control register – CRC error does not execute command and sets ALARM
• 0x57 Write configuration register – CRC error does not execute command and sets ALARM
• 0x58 Write DAC gain calibration register – CRC error does not execute command and sets ALARM
• 0x59 Write DAC zero calibration register – CRC error does not execute command and sets ALARM

For these commands, the CRC error status is not checked, and the command execution is not blocked

• 0x56 Write reset register - Execute command even with bad CRC (reset is 0x56 0x00 0x01 0x5E)
• 0x95 Watchdog timer reset - Execute command even with bad CRC
• 0x96 CRC error flag reset - Execute command even with bad CRC
• 0x02 Register read - Execute command even with bad CRC

This was checked against the RTL code. For the reset commands, I think design intended that if there was a problem, the device would be easily reset without the CRC. I’m not sure why the device was designed not to check the CRC for the register read.

Joseph Wu

ttd,

The software reset should be rather fast, but yes, if you are able to read back the default 0 bit of the reset register, the device should be done.

Joseph Wu

ttd,

I did talk to one of the digital designers. He said that said that you should not look to read back from the reset register to check the reset time. A more valid way of checking the reset is to read back from a different register that has been set to a non-default value to see that the reset is back to the default value. This would be a better way to check the reset completion.

However, to after writing to the reset register, there is a delay of a few hundred microseconds to complete the reset. This is based on an analog circuit that would take a maximum of 400us to complete. From the digital, the reset would take less than 10us to propagate to the registers. The sum of these times would be the total time to complete the reset.

The issue of a NOP command after a reset command is not necessary. We recommend issuing a NOP command after power up because there may be unusual transients on the SPI signal lines after power up that might be interpreted as communication. Unless there are unusual transients at the digital lines, the NOP is not needed.

Joseph Wu

ttd,

NOOP and NOP are the same thing.

Q12
The use of the NOOP is specifically when the first command is to enable the CRC after powering up the device. This is to make sure the SPI clock and frame are aligned. If the first command is to send a reset, followed by the enable of the CRC, then the NOOP is not needed.

Q13
I would connect unused pins in the following way:
/ALARM - Leave this pin floating
BOOST - Leave this pin floating
CMP - Leave this pin floating
HART-IN - We recommend tying this pin to ground through a 22nF capacitor. This is to AC couple the pin to ground to prevent any EMC/EMI noise.

Q14
The thermal pad should be connected to AVSS supply. For best thermal performance, you would want to connect this pad to a power plane on the PCB board. Typically this would be a large inner layer of copper used for the AVSS supply. Using this power plane connection draws heat from the device to the power plane where it can easily be dissipated.

Q15
I did find this TI document on PowerPAD layout guidelines (www.ti.com/.../sloa120.pdf).
The PowerPAD is similar to the thermal pad on the bottom of the device. The document recommends an x-ray to verify that 50% of the thermal pad is soldered and the there is less than 50% voiding. This is described on page 4.

Q16
As I understand, vias can quickly wick away solder and create more voiding in the soldering process. If the vias are filled, plugged, or tented, then the solder may not easily pull out from under the thermal pad to create the voiding. So yes, sealing the via would be best to prevent any voiding or coverage problems.

I would say that vias are not fundamentally necessary. However, as mentioned previously a via connection to a power plane helps with power dissipation on the device. I use vias for all thermal pads. I can't really think of a case where I wouldn't use vias in the layout in the thermal pad.

Q17
When the power is cycled on/off, the device goes through a power-on reset cycle, which is functionally similar to a reset. In this case, the IOUT/VOUT code returns back to 0, and the output returns to a high impedance state.

Q18
I don't have any information on the design range variation of the short-circuit current. It's not a parameter we design for, except to make sure that the short circuit current is not destructive.

Joseph Wu

ttd,

Q15:  First, the PowerPAD layout guidelines document does say "TI recommends placing thermal vias in the solder mask defined thermal pad to effectively transfer heat from the top copper layer of the PCB to the inner or bottom copper layers." I would do this for the DAC8760 because the power dissipated from the device could potentially be high. As for via recommendations, I would use the filled or plugged vias. I think the PowerPAD recommendation just acknowledges the fact that this may add extra cost to the PCB. However, document does say that unplugged vias may prevent solder loss and protrusions. Here, I would go with the DAC8760 recommendation. It would not damage or have a bad effect on the PCB.

Q17:  When the power is off, I would consider the DAC IOUT/VOUT to not be in a high impedance state. When there is no power, the circuit is not biased normally. Additionally, when the power is 0V and you try to drive the output, the current may be sunk into the ESD diodes connected to the supplies. With the diode, this extra current turns on as the output voltage is driven ~0.7V beyond either supply (which is set at 0V with no power). 

Joseph Wu

ttd,

Q18. The CMP pin is an internal node to the output buffer of the DAC. This node is a Miller compensation connection that is used to increase the capacitive load drive of the output. Some designers have seen that this node may be susceptible to damage when there are electrical fast transients (EFT) at the output. We've noted that higher capacitances can couple in more charge and creates damage, while lower capacitances

One of the previous applications engineers had tested this and noted that no damage was seen at 470pF or below. However, with higher capacitances, damage could be avoided by the placement of the 100pF capacitance from CMP to ground. I believe that this extra capacitance creates a small voltage divider to keep the CMP pin latched near ground and prevents the pin from a receiving an EFT spike. I'm not sure about effect of this extra capacitance. This may reduce the overall bandwidth of the output drive even more than the original CMP capacitance, but I don't think that this would be very large if an effect.

Q19. This circuit is a current limiter that prevents excess current from being pulled from VIN. The bulk of the current flows from Q1 to Q2 through D1. R1, R2, and R3 are all biasing resistors. R1 limits the current going into Q2 while R2 can only take so much current from Q1. D1 prevents the a reverse current from flowing through the circuit.

Q20. I don't have a settling time diagram for a circuit with the 1nF capacitance and the 100pF capacitance.

Q21. If the control registers are in the default state, the DAC code write still takes place. However, at the default state the DAC output is not enabled, so the user will not see a change at the output.

Q22. I'm not exactly sure what happens when the device is not in CRC mode and the user tries to put in a 32-bit communication frame with the CRC byte. My guess is that the communication does not work. I believe that the input shift register for DIN overflows because it is expecting a 24-bit communication. In that case the device thinks that the communication is the last 24 bits of the 32 bits that were sent. Depending on the data that was sent, it's likely that the communication will not be interpreted as a command and then ignored.

Out of curiosity, who is this customer, and what is the application?

Joseph Wu

ttd,

Sorry, I meant to say that lower capacitances coupled in less charge and did not damage the device.

Joseph Wu

ttd,

Q17: 

ttd said:

→Regarding the part stating “when the power is 0V and you try to drive the output,” is it correct to understand that if a voltage higher or lower than the DAC's     GND level is applied externally to the Vout terminal, a voltage drop occurs through the built-in ESD diode in the DAC?

That is correct. When the supplies are at 0V (equivalently ground) and the output is driven, current may be sunk or sourced from the built-in ESD diodes at the output as either diode is forward biased.

Q20: 

ttd said:

→Is it correct to understand that increasing the capacitance of the CMP terminal, as shown in the figure below, will result in a trend like the red line(I drew on Figure 7-38. VOUT Settling Time vs LOAD)? Since we would likely need to adjust the actual device if no characteristic diagram is available, I would like to understand the relationship between the CMP terminal and responsiveness.

I haven't seen any characteristic curves for the settling time with the CMP capacitance except for the curves in the data sheet. I would guess that the flat portion would be higher because it takes a longer RC settling time, and that it moves the slope to the right. However, I don't have any data on that. Note that 470pF is the highest capacitance used for CMP alone. With higher values of the CMP capacitance, you should use a 100pF capacitance to ground.

There isn't any specific method of selecting the capacitor except through experimental means. Again, this capacitance is a Miller capacitance so it uses the gain of the output stage to create the first pole to slow down the bandwidth. The frequency would be dependent also on the load used at the output.

Q22:

ttd said:

→When the DAC is set with CRC enabled, what value is sent to the DAC data register after the DIN receives 24-bit data and the LATCH is updated?
When the internal configuration is CRC enabled (32-bit), is the data rejected if the specified SCLK is not present?

When the DAC is set with CRC enabled and a value is set to the DAC data register without the CRC, I would guess that this would flag a CRC error and the device would reject the data. Here the DIN shift register has 1. Not been filled completely and 2. Not received a correct CRC value.

Joseph Wu

ttd,

Q23. I think pattern 1 is enough. The reason to disable the output is to make sure the buffer and the operating point is cleared from the output of the DAC. By setting the output enable to 0, you clear the operating point. After that, you should be free to change the output range and reset the output.

I would note that the glitches may also be a function of any capacitance connected to the output buffer. If there are any capacitances on the output or even in the CMP capacitance, you would need these capacitances to discharge to make sure the output buffer is starting up cleanly, without previous configuration of the output.

Q24. I would probably do something different. I think it would be better to just read back the configuration register that has the CRC setting. With the CRC enabled, the sequence to read the register would be: 0x02 0x00 0x0B 0xE7. If the CRC is set, then you would read back 0x00 0x00 0x08 0x38. Any read other than the previous response would indicate a problem in the CRC. Either the SPI is interrupted, shown by the CRC, or the device has been reset or powered off and on.

However, if the sequence is:
　　(1) 24-bit read command
　　(2) 32-bit write command
　　(3) 32-bit read command

At (1), the read command only works if the device was reset. If the device is in CRC mode, then I think the device returns 0xFFFFFF. At (2), if the device is in CRC mode, then the write will occur. If the device has been reset, then this write command will not occur. At (3), the same occurs, either the read occurs with the CRC enabled, and the read does not occur with the device reset.

Again, I think it would just be simpler to read back the configuration register. If the read is correct, then the device should be fine. If the read is incorrect, either there's a problem in the CRC response, or the device has been reset.

Joseph Wu

ttd,

Q24. The SDO is Hi-Z when the LATCH pin is high. Whenever LATCH is low, the output may be undefined. This means that the output pin is driven, but the value may be random (or possibly the repeat of the previous command). If the read back of the configuration register is correct, then you know that the CRC is enabled. If the output does not come back correct, then there it is likely that the CRC was somehow disabled.

Q25. When setting the CRC mode in the configuration register, the change is immediate. You should need to only wait the minimum high time (t5 is 40ns) for the LATCH pin before communication of the next frame.

Joseph Wu

ttd,

Q24. I'm sorry I didn't explain that clearly. I was referring to the Readback Mode Timing from Figure 7-2. My point was that clocking out data should be done as shown in the diagram with two different frames.

First, there should be a read frame, and then a NOP frame to clock out the data. During the read frame with the SDO, the data is undefined. Because of this I would not use a read frame and then another successive read frame to clock out the data. What the diagram does not show is that SDO is not Hi-Z when LATCH is low. Again, I would always use both a read frame and a NOP frame to read back data from a device.

Q26. The 200uA value is the value used in final test to check the VOH and VOL levels. I'm sure the device can do sink and source more current, but I don't have any information on the amount of current that it can drive. I would guess the maximum level is very close to what a photocoupler would require, but with different conditions, this might change. Because of this, I wouldn't connect it directly and use a buffer.

Q27. I would again refer to the Readback Mode Timing from Figure 7-2.

At the NOP used to clock out the read data, the data sheet specifically says that the first eight bits should be treated as don't care and does not label it directly as the return address. I believe there are cases where these bits could be set differently, and would not rely on them to return the read address.

Joseph Wu

ttd,

Q24. A NOP is basically a "no operation" command. It is the red box that you enclosed in the copy of Figure 7-2 that I had used in the previous post. In the DAC8760 it is at address byte 0x00. To execute the NOP, you send in 0x000000 to the device (0x00000000 if CRC is enabled).

The NOP is used to clock out the data when a read register command is sent. That is basically its only function. The point is that during a read, you do not want to be using another command to clock out the data. The customer's sequence is fine. In their sequence, it seems they want to write to registers and readback the registers that were written. When they do read back the registers, they should just make sure they use NOPs to clock out the read data.

Q28. For these registers, the NOP, the read operation, the RESET, the Watchdog timer reset, and CRC fault are not registers that are readable. For the configuration register (bits 15:11) and the status (bits 15:5), they are either don't care or reserved. This means they should not be used for anything by the customer. I don't think they are programmed to output anything in particular and the output may be random.

Joseph Wu

ttd,

I'm not sure I fully understand your question. In Figure 7-2, the figure shows a NOP (labeled as NOP condition) to clock out the data. Also, in the section for Read Operation (section 8.5.1.3, p40). The data sheet says to "Follow the read operation with a no-operation (NOP) command to clock out an address register".

I'm basically stating that during a read of the device register, you should always use the NOP to clock out the data after the read command. You should not use any thing else to clock out the data during a read.

If the device receives something other than a NOP, I'm not aware of any other data that comes out of the data read other than what was intended to be read. However, the data sheet specifically says to use the NOP and I'm not going to recommend something other than what the data sheet says.

Joseph Wu