This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AMC1336: CLKIN duty cycle limits

Part Number: AMC1336

Tool/software:

Hello everyone,

the datasheet specifies that the typ. CLKIN duty cycle is 50%. The limits for CLKIN are speficied with min 40% and 60% max. 

What would happen if these values were not fullfilled, for example, a positive duty cycle of 30% was used?

Does this affect the overall function, or does the ADC simply become inaccurate?

Thanks all lot in advance!

Andreas        

  • Hello Andreas,

    As long as the CLKIN frequency remains constant, and only the CLKIN duty cycle violates the timing, the device remains operational but the performance deteriorates. In general, SNR and THD will be affected more you go over the bounds. When the clock frequency is outside of the bounds, the device may stop operation completely as some internal checks might be falsely triggered.

    However, I can't get you exact data by "how much" it goes worse as I do not have any data for testing outside of the specification.

    I hope this helps,

    PS: Please note that there are architectural differences between various AMC products. For this reason, this answer is valid for AMC1336.

    Best regards,

    Jiri Panacek,

    Systems Applications Engineer, Isolated Converters

  • Hello Jiri,

    thanks a lot. This information will help. 

    Andreas