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DAC34SH84: Issue Reading Register 4 on DAC34SH84 During IO Test

Keerthana N
Prodigy 160 points
Part Number: DAC34SH84


Tool/software:

Hello,

I am currently working with the DAC34SH84 and testing the IO Test feature. I have hardcoded the DAC input values to 0, and I’ve also set the IO Test value to 0. However, when I attempt to read Register 4, I am not getting a value of 0 as expected.

Additionally, I followed the suggestions in this forum post:
https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/218923/dac3484-misbehavior

Despite following the instructions there, I am still not getting the correct value from Register 4. When I read Configuration Register 5, I noticed that Bit 7 is set to 1.

Could anyone please help me understand what might be going wrong? Any insights would be appreciated.

Thank you!

  • 0
    TI__Guru* 79204 points

    Hi Keerthana,

    The best way to troubleshoot this is for you to draw up the timing diagram of all the I/Q signals that you are sending from the FPGA, and the actual captures on the RTL. 

    The results are OR of the Channel AB and Channel CD LVDS bus. Therefore, you will need to make sure all 32 lanes are truly sending 0 pattern.

    Please also send your programming sequence to enable the IO Test Feature.

    -Kang