Other Parts Discussed in Thread: DAC38J84, ADC12QJ1600,
Tool/software:
Dear Team,
I hope this message finds you well.
I am currently working with the ADC12QJ1600AAV and DAC37J84IAAV devices from Texas Instruments. I have reviewed the documentation regarding the calculation of SYSREF and FPGA CORE CLOCK. While I was able to apply the calculation methods for the ADC, I would like to verify whether the same formulas or calculation approaches also apply to the DAC, particularly for determining the Lane Rate, SYSREF, and FPGA CORE CLOCK for the DAC37J84IAAV.
Could you kindly confirm if the calculation methods remain consistent between the ADC and DAC, or if there are any differences I should be aware of? I would greatly appreciate your guidance or any relevant documentation or examples pertaining to the DAC as well as ADC for the calculations.
For your reference, below are the calculation formulas I have been using for the ADC in JMODE = 0:
|
ADC Calculation (JMODE = 0) |
Remarks |
|
|
SerDes Linerate ( fLINERATE ) |
Fs × R |
Fs = 1GHz; R = 8; |
|
SYSREF |
(R × Fclk) / (10 × F × K × n) |
R × Fclk = fLINERATE; F = 8; K = 4 (K = 4:4:256); n = 1; |
|
FPGA Clock |
fLINERATE / 40 |
FPGA Clock = 200MHz |
|
fLINERATE / 80 |
FPGA Clock = 100MHz |
|
Thank you very much for your support.
Regards,
Liston
