ADS8365: Need details about EOC

Rajaram Amarnath

Part Number: ADS8365

Tool/software:

Hi,

We are using ADS8365 in our project. We have used all 6 input channels and shorted all 3 Hold signals and making it low for one clock cycle to start the conversion.

We are reading the channels one by one by providing each channel address (Not in FIFO mode or Cycle mode).

My question is

1. We are observing two or three EOC after 16 clock pulses. Is it normal to get more than one EOC?

2. We are providing clock pulse for hold and conversion (20 clock pulses after hold). Do we need to provide clock for reading the digital data from the register after EOC?

Thanks

Rajaram A

4 months ago

0 Tom Hendrick 4 months ago

TI__Guru**** 181981 points

Hi Rajaram,

Can you provide a schematic and perhaps a timing diagram of your control signals? The clock input to the ADS8365 is meant to be a continuous clock, how are you sourcing that on your end? If all HOLDx pins are tied together, you should only see one EOC for each channel pair.

0 Rajaram Amarnath 4 months ago in reply to Tom Hendrick

Prodigy 30 points

Hi Tom,

We are sourcing the ADC clock from our FPGA. We are providing only 30 clock pulses (1MHz) after Hold signal.

After 16 clock cycles we are getting EOC (Twice or Thrice). Then we are providing the CS and RD to read the data from register.

I have attached the timing waveforms. Pls check.

ADC Waveforms.zip

0 Tom Hendrick 4 months ago in reply to Rajaram Amarnath

TI__Guru**** 181981 points

Thank you Rajaram,

Slight revision to my initial reply, there should be one EOC per channel pair. Can you make that HOLDx pulse 1.5 clocks wide so that it catches the rising edge of the clock and see if you get more consistant behaviour?

0 Rajaram Amarnath 4 months ago in reply to Tom Hendrick

Prodigy 30 points

Hi Tom,

We did alter the hold and ADC clock. Now rising edge of the Hold is catching the clock. Still the behavior is not as expected.

Can you confirm

If the clock is needed to read the data from register?

We are getting three different data when we provide CS and RD. Is it normal?

Can you confirm the CS and RD timing?

I have attached the waveform for your reference.

ADC Wavefoms.zip

Thanks

0 Tom Hendrick 4 months ago in reply to Rajaram Amarnath

TI__Guru**** 181981 points

Rajaram,

Please review Figure 1 in the datasheet and compare that you your "Read & Chip select" diagram. The rising edge of RD while /CS is low is what should strobe valid data to your controller.

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ADS8365: Need details about EOC