ADS124S06: Can I use Constant Current Measurement for Two RTDs

Hi ASISH KUMAR SINGH,

Please review our RTD design guide for more information. Specifically section 2.9, "Multiple 2-wire RTD Measurements: https://www.ti.com/lit/an/sbaa275a/sbaa275a.pdf?ts=1754491064351&ref_url=https%253A%252F%252Fwww.google.com%252F

This section answers your question directly

-Bryan

Hi ASISH KUMAR SINGH,

As I mentioned in your other post, you cannot pull SCLK high. SCLK needs to idle low

Typically the common mode caps e.g. C11 and C15, are sized 1/10 to 1/20 compared to the diff cap e.g. C12. This is to keep tolerances in the common-mode caps that result in common-mode noise turning into differential noise

100nF is probably too large on the inputs, but that is a design decision for you to make. Of course you can always reduce this size later if you run into issues, so I don't think you need to do anything now

You do not need R4, C2, and C4 on the REF inputs. 

I don't see an issue connecting the two RTDs to the same connection point. This is commonly how RTD measurements are made. You can add a mux if you want and control that mux using one of the ADC GPIO pins. Also, you are using 2-wire RTDs, which is the lowest accuracy RTD configuration.

-Bryan

Hi ASISH KUMAR SINGH,

Please see here: https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/886352/faq-ads124s08-when-should-i-enable-disable-the-external-reference-buffers

No you should not remove R6 or C3, that is why I told you to only remove the other components

-Bryan

Hi ASISH KUMAR SINGH,

You asked a similar question in this post, and it was answered as completely as possible: https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1548445/ads124s06-what-is-the-effect-of-using-voltage-reference-method-in-place-of-constant-current-source-method/5958158?tisearch=e2e-sitesearch&keymatch=%252520user%25253A657217#

We also provided you a tool to help estimate accuracy in your system. You also don't seem to be taking any of our recommendations, because every schematic you have provided us you still have SCLK tied high

I'm not sure how else to support your requests

-Bryan

Hi ASISH KUMAR SINGH,

Those components and the documents you are referencing are generally used for electrical overstress (EOS), not ESD. This is when a constant overvoltage is applied to the inputs. For example, the installer miswires a module's inputs and applies the 24V power supply voltage directly to the 5V-only ADC input pins.

For ESD, use ESD or TVS diodes to mitigate this high-frequency, short-duration energy

AINCOM is just like any other analog input, there is no special requirement for this pin

REFOUT does not need to be connected to anything (other than the required capacitor), unless you want to use the ADC VREF voltage to bias some external sensor for example

-Bryan

Hi ASISH KUMAR SINGH,

This looks like it should work, but of course you will have to make the final determination on your schematic.

The RC components seem okay, though 100nF seems high to me. As I mentioned previously, you can always change these values later, so I wouldn't worry about the exact values right now

You should only have a single resistor and capacitor on RREF, I mentioned this in my post on August 7. 

-Bryan

Hi ASISH KUMAR SINGH,

I assume you meant "resistor" in your last post? If so, then yes you can add a resistor in the IDAC path to help limit the current. Again, this resistor might not help too much against transients such as ESD, but it will help limit the current for EOS events

-Bryan

Hi ASISH KUMAR SINGH,

From what I can see the circuit generally looks okay. I mentioned in another post that you should remove C28 and C7 from the reference inputs

I'm also not sure you need so many capacitors on your inputs, but of course you can always remove them later if they are disturbing the measurement

-Bryan

Hi ASISH KUMAR SINGH,

There will be some settling time as you switch the current source from one channel to the next. The settling generally depends on how much capacitance you have connected to the IDAC pins. You will need to determine this experimentally. You can then use the ADC internal programmable delay to account for this settling.

Yes, you can use both IDACs in series. See section 2.7 in this document for more information: https://www.ti.com/lit/an/sbaa275a/sbaa275a.pdf?ts=1757451613876&ref_url=https%253A%252F%252Fwww.google.com%252F

-Bryan

Hi ASISH KUMAR SINGH,

Some comments:

• Remove the connections from DGND and AVSS to the thermal pad. I circled these in the image below. Instead, make the ground connection through the decoupling capacitor. This is effectively how you have it already on the AVDD caps at the bottom left of the image, where each cap has a ground connection and you run a trace from AVSS to the cap ground. For that one, you just need to remove the connection to the thermal pad. For DVDD, you will need to remove the connection and add a new one since there is no ground connection at the cap
• I'd add some more vias connecting the top layer ground pour to the bottom layer (I assume there is also a ground pour there). I marked some of these as X's on the image below. You don't want to have long pieces of copper that are basically just floating or these will act like antennas. Again, I marked some but not all, you will have to make that determination

From what I can see the rest looks okay, but of course you will need to make the final judgement call

-Bryan