Tool/software:
Hello,
we have ADC12QJ1600EVM with Zynq FPGA using TI JESD204 IP HDL stack. The settings are JMODE3 (10bit resolution), Fs=500Msps, F=5, K=32. The FPGA design uses just one RX lane. It seems to be somehow working, QPLL is locked, rx_lane_data_valid is 1 so the FPGA accepts the data. I use the Ramp test mode for the first trials. The datasheet states that the ramp runs from 0x00 to 0xFF per octet. However, I see that it runs only from 0x00 to 0x9F. Is this correct or wrong for my mode of operation?
Thank you in advance,
Michael
0x9D9E9F00 0x999A9B9C 0x5060708 0x1020304 0xD0E0F10 0x90A0B0C 0x15161718 0x11121314 0x1D1E1F20 0x191A1B1C 0x25262728 0x21222324 0x2D2E2F30 0x292A2B2C 0x35363738 0x31323334 0x3D3E3F40 0x393A3B3C 0x45464748 0x41424344 0x4D4E4F50 0x494A4B4C 0x55565758 0x51525354 0x5D5E5F60 0x595A5B5C 0x65666768 0x61626364 0x6D6E6F70 0x696A6B6C 0x75767778 0x71727374 0x7D7E7F80 0x797A7B7C 0x85868788 0x81828384 0x8D8E8F90 0x898A8B8C 0x95969798 0x91929394 0x9D9E9F00 0x999A9B9C
