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ADS9227: SMPL_CLK to FCLKP time

Kevin Mitchell
Prodigy 10 points
Part Number: ADS9227
Other Parts Discussed in Thread: ADS9229, ADS9228

Tool/software:

Hi

Section 6.7 of the ADS9227 datasheet lists the parameter Td_SMPL_DATA  (Time delay: SMPL_CLK falling to FCLKP rising) as a minimum of 103ns and a maximum of 112ns.

Would it be correct to say that this value is only true when operating  with a clk output period of 4.167ns and with a 24bit output word format? (24 x 4.167ns =100ns approx) . The paragraph preceding the table does say "maximum throughput", so I'm assuming that there is 3ns to 12ns of additional latency.

Would it then be correct to say that the additional latency is therefore independent of data link configuration and this 3ns -12ns would apply to any configuration of the ADC?

Many thanks for your help!

  • 0
    TI__Expert 3660 points

    Hello Kevin, 

    Welcome to TI's E2E forum! Thank you for posting your question! 

    Unfortunately the Td_SMPL_DATA  in Section 6.7 of the datasheet appears to have a typo we missed during the latest update of this datasheet. The order in that row should be reversed, or at least swap the values between the ADS9229 & ADS9227.

    ADS9229 = 106ns to 112ns 

    ADS9228 (correct) = 186ns to 196ns

    ADS9227 = 370ns to 378ns

    I have started an action internally to fix this error in the datasheet, thank you for bringing it to our attention!

    To address the delay question: Td_SMPL_DATA represents the time between the falling edge of SMPL_CLK (start of conversion for sample N) and the rising edge of FCLK when the corresponding MSB for sample N appears on DOUT. 

     For this family of devices the latency is dependent on the SMPL_CLK frequency, data frame width, as well as some additional timing latency.   You are correct about the additional latency, we did find that using 12ns as a max value could encompass the expected additional latency in most configurations. 

    Similar to the 18-bit versions of this family of devices the output latency is calculated as follows: 

    for the ADS9227: 

    Td_SMPL_DATA = 1.83 x t_SMPL_CLK + t_LAT = 1.83 x 200ns + 12ns ~= 378ns

     

    Please do take this delay into account when aligning data capture to data output in your system. 

     

    Best regards, 

    Yolanda

  • 0 in reply to Yolanda Gonzalez
    Prodigy 10 points

    Thank you Yolanda!