ADS7952: ADS79xx looking for HDL behavioral model for FPGA simulation

As I see it - HDL behavioral model for helping customers integrate TI's products into products - is a very important selling tool.
It is fairly easy to do - with the current AI tools - just open a git project for doing so - and let AI fill it...
Once you find an error - fix it :-)

The Idea is very simple - The task is to write the FPGA code that glue the CPU to the ADC.
So I write a Test Bench to test my implementation and to give the software guys instructions on how the hardware works.
In this test bench I connect my FPGA design ( the CPU interface to an SPI ) to a "behavioral model of the hardware" that include a behavioral model of the ADC.

This test bench then runs in an HDL simulator and show a "success" if the test passed.
Then the software can do the same steps as the test bench and have a good chance of actually working in production...

Hi David,

Input data format for manual mode looks correct, but I would try configuring the SPI peripheral as SPI Mode 0 (CPHA = 0, CPOL = 0). Given that, the device might only be seeing 15 clocks.

Regards,
Joel

Thank you for your reply - I did what you suggested and now it works better.
This is my current version for a behavioral model for the ADS7952 - hope it make sense  ....

// ADS7952_model.sv
// Behavioral model for the Texas Instruments ADS7952 ADC
// Modified to better reflect the one-frame delay for manual mode programming as per the datasheet.

`timescale 1ns / 1ps

module ADS7952_model (
    output SDO,
    input  CS,
    input  SCLK,
    input  SDI,

    inout [ 3:0] GPIO,
    input [11:0] adc_in[11:0]
);

    // Internal state
    reg [15:0] shift_reg;
    reg [ 3:0] bit_count;
    reg        SDO_out;
    reg        sdo_oe;
    
    reg [ 3:0] adc_channl_requested;     // in the end of first transaction we know what channel to sample

    reg [11:0] adc_mem_sampled;          // after 2ed CS neg edg -> we sample the adc of adc_channl_requested in the previos transaction  
    reg [ 3:0] adc_channl_in_convertion; // after 2ed CS neg edg -> move the adc_channl_requested here

    reg [11:0] adc_mem_ready2send;       // after 2ed CS pos edg -> move the adc_mem_sampled to ready for sending in the 3ed transaction 
    reg [ 3:0] adc_channl_ready2send;    // after 2ed CS pos edg -> move the adc_channl_in_convertion here
    
    reg        auto_mode;

    // GPIO registers
    reg [ 3:0] gpio_dir; // 0 = input, 1 = output
    reg [ 3:0] gpio_out;

    // GPIO output enables
    assign GPIO[0] = gpio_dir[0] ? gpio_out[0] : 1'bz;
    assign GPIO[1] = gpio_dir[1] ? gpio_out[1] : 1'bz;
    assign GPIO[2] = gpio_dir[2] ? gpio_out[2] : 1'bz;
    assign GPIO[3] = gpio_dir[3] ? gpio_out[3] : 1'bz;

    assign SDO = sdo_oe ? SDO_out : 1'bz;

    // Initialize memory and registers
    integer i;
    initial begin
        
        auto_mode     <= 0;
        sdo_oe        <= 1'b0;
        shift_reg     <= 16'd0; 
        bit_count     <= 0;

        // Default GPIO to input
        gpio_dir      <= 4'b0000; // All inputs
        gpio_out      <= 4'b0000;

        #1;        
        adc_channl_requested     <=  4'hB;
        adc_mem_sampled          <= 12'hDED;
        adc_channl_in_convertion <=  4'hB;
        adc_mem_ready2send       <= 12'hDED;
        adc_channl_ready2send    <=  4'hB;
    end

    // At the start of a transaction, load the shift register with the result
    // of the *previous* conversion cycle (for the current_channel).
    always @(negedge CS) begin
        // Start of a new transaction
        bit_count       <= 0;
        sdo_oe          <= 1'b1;

        // Load the shift register with the result of the previous conversion
        shift_reg       <= { adc_channl_ready2send, adc_mem_ready2send };
        SDO_out         <=   adc_channl_ready2send[3];
        // The input signal is sampled with the falling edge of CS:
        adc_mem_sampled <= adc_in[ adc_channl_requested ];
        
        // requested  -> convertion
        adc_channl_in_convertion <= adc_channl_requested;
    end

    // At the end of a transaction, decode the command that was just received
    // and set up the state for the *next* transaction.
    always @(posedge CS) begin
        // End of transaction
        sdo_oe  <= 1'b0;
        SDO_out <= 1'b1;

        // next ADC step
        // convertion -> ready
        adc_channl_ready2send    <= adc_channl_in_convertion;
        adc_mem_ready2send       <= adc_mem_sampled;

        // Decode the command received on SDI
        case (shift_reg[15:12])
            4'b0001: begin // Manual Mode (DI15-12 = 0001)
                auto_mode          <= 0;
                // DI11 = 1 enables programming of ‘range and GPIO’
                if     (    1'b1  == shift_reg[11  ] ) begin
                    adc_channl_requested <= shift_reg[10:7]; // DI10-7 = binary address of channel
                        //           shift_reg[ 6  ]; // 0 = Vref    1 = 2*Vref
                        //           shift_reg[ 5  ]; // 1 = power down
                        //           shift_reg[ 4  ]; // in next transaction  0 = output samples channel  1 = output GPIO
                    gpio_out             <= shift_reg[ 3:0]; 
                end
            end

            // Other modes (like Auto-1) would need to be defined based on their DI15-12 patterns
            // If no other patterns are defined, they would fall into a default case.
            default: begin
                // Handle unimplemented or reserved commands
            end
        endcase

        // After decoding, update the current_channel for the next conversion cycle.
//      if (auto_mode) begin
            // In auto mode, channel increments after each conversion.
            // The programmed_channel is ignored.
//          current_channel     <= (current_channel == 11) ? 0 : current_channel + 1;
//      end else begin
            // In manual mode, the next channel to be converted is the one we just programmed.
//          current_channel     <= programmed_channel;
//      end
    end

    always @(posedge SCLK) begin
        if (!CS) begin
            // Shift data in on SDI and out on SDO
            shift_reg <= { shift_reg[14:0], SDI };
            bit_count <= bit_count + 1;
        end
    end
    always @(negedge SCLK) begin
        if (!CS) begin
            if ( sdo_oe ) begin
                SDO_out <= shift_reg[15];
                
            end else begin
                SDO_out <= 1'b1;
            end;
        end
    end

endmodule