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ADS1261-Q1: ADS1261 – Getting Zero Output in 3-Wire RTD Measurement with Universal Low-Side Reference Circuit

Part Number: ADS1261-Q1
Other Parts Discussed in Thread: ADS1261

Tool/software:

Hello,

I am working with the ADS1261 to measure a 3-wire PT100 RTD using the universal RTD circuit with low-side reference described in the TI RTD Reference Design Guide. My setup uses:

  • Reference resistor: 350 Ω between REFP0 and REFN0

  • RTD connection: AIN2, AIN3, AIN5 as per TI’s 3-wire low-side reference schematic

  • Capacitors: 220 nF from each analog input to AVSS as shown in TI’s circuit diagram

  • IDAC configuration: IDAC1 and IDAC2 both set to 3 mA and routed to AINCOM

  • Reference setting: Internal reference enabled (REF register: RMUXP=10, RMUXN=10, REFENB=1)

  • Mode: PGA bypassed, SINC1 filter, 1200 SPS, pulse conversion mode, chopping enabled

The initialization sequence is:

  1. Configure REF, PGA, MODE0..3, IMUX, IMAG, INPMUX registers

  2. Route IDAC currents to AINCOM

  3. First measurement: AIN2 – AIN3

  4. Second measurement: AIN3 – AIN5

  5. Final RTD value = (first reading – second reading)

The problem:
Even though the actual RTD resistance is ~330 Ω and I measure ~1.79 V across it with a multimeter, the ADS1261 conversion always returns 0 (status byte + all data bytes 0x00), except for the status byte which shows 0x04.

Questions:

  1. Could the 220 nF input capacitors be causing the ADC to output zero if I don’t allow enough settling time?

  2. With this topology, should I be using the internal reference (REF register) or routing to the external reference resistor voltage?

  3. Is there any additional settling/conversion sequence required when switching the INPMUX channels in this universal RTD circuit?

  4. Are there any known issues if START pin is held low and conversions are started via command mode only?

Any insights on what could be causing constant zero readings would be greatly appreciated.

Thank you,
Prashant V Achari

  • Hi Prashant Achari,

    Can you provide us logic analyzer captures showing the data communication between the ADC and the controller? Please include the CS, DOUT, DIN, SCLK, and DRDY signals. I'd like to see the WREG, RREG, and RDATA commands, as much as you can send me. If you have a Saleae logic analyzer you can send us the .sal file

    Make sure that the plots are labeled so we can clearly understand which signal is which

    -Bryan

  • Hi Bryan,

    I have attached the .sal file capturing details about ADC init and ADC data capture, please review.

    Thanks and regards

    Prashant V Achari

    .ADS1261RTDoutput.zip

  • Hi Prashant Achari,

    Thanks for sharing the requested information

    In your saleae capture you are triggering on the wrong edge (rising, whereas you should be triggering on the falling edge). This is not a problem if it's just the Saleae (the data can be wrong, but that's easy to fix). If your controller is triggering on the wrong edge however that won't work, and the ADC communication will be broken

    You can see this in the image below (note that I switched to triggering on the falling edge) where the value on DIN is not the same as the response on DOUT.

    Can you please make sure you are triggering on the correct edge, otherwise the communication will not always work.

    You can also try enabling the CRC to make sure there are no communication errors

    -Bryan