Tool/software:
We are transmitting 170Msps x 64 across two JESD lanes as shown below (16 bit I/Q for each of two DAC outputs)
My assumption is that the JESDCLK should be 170MHz (divide by 4, config37=0x4000) as shown below.
However, it must be set to 340MHz (divide by 2, config37=0x2000) to work.
Hello David,
The quick start page, once you enter the needed configuration for the DAC38j84, will automatically configure the JESD CLK for you. The clkjesd_div setting is all calculated.
Depending on the JESD204B configuration setting of the JESD204B RX logic block, the reference clock to the JESD204B RX logic block will need to be adjusted accordingly. Please refer to Table below for details on the clock divider setting.
|
DAC3xJ8x JESD204B RX Logic Clock Divider Setting |
|||||
|
Config37, bit15 to 13, clkjesd_div |
|||||
|
Interpolation |
|||||
|
LMF Mode |
1x Int |
2x Int |
4x Int |
8x Int |
16x Int |
|
841 |
2 |
4 |
8 |
16 |
32 |
|
442 |
1 |
2 |
4 |
8 |
16 |
|
244 |
NA |
1 |
2 |
4 |
8 |
|
148 |
NA |
NA |
1 |
2 |
4 |
|
821 |
4 |
8 |
16 |
32 |
N/A |
|
421 |
2 |
4 |
8 |
16 |
32 |
|
222 |
1 |
2 |
4 |
8 |
16 |
|
124 |
NA |
NA |
2 |
4 |
8 |
Ok, I understand, thanks.
The Quick Start page assumes that the DACCLK is not translated in freq by the PLL (N divider divides by 2, prescalar multiplies by 2) as shown below.
I thought I needed to recalculate everything on this page given my lower freq input DACCLK and my SERDES REF derived from PLL Clock.
However, I needed to recalculate everything *except* the JESDCLK divider.
Thanks for clearing that up.
Dave
