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ADS8556: When BVDD(+3.3V) is turned on, why does AVDD（+5V) rise even though it is turned off?

Shinichi Inoue
Guru 21881 points
Part Number: ADS8556


Tool/software:

Dear Specialists,

My customer is evaluating ADS8556 and has a question.

I would be grateful if you could advise.

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The board I'm currently evaluating uses an ADS8556IPM.

I measured the startup waveform of the analog power supply for ADS8556.　

I found that when BVDD (3.3V) is powered up, the 5V appears to gradually rise before the +5V power supply is turned on.

This rise timing coincides with the turn-on of the +3.3V.

Is it correct to understand that this is due to the internal structure of the ADS8556, where the voltage of the power supply that was powered up first leaks into other power supply circuits?

Could you please let me know why the AVDD is rising at BVDD is power up.

Question about ADS8556 .pdf

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I appreciate your great help in advance.

Best regards,

Shinichi

  • 0
    TI__Genius 9476 points

    Hi Shinichi-san,

    Thanks for your post.

    Could you provide a scope shot of BVDD also so I can compare the ramp to AVDD?

    I am thinking AVDD ramp is due to some back flow from the BVDD rail through the ESD cell, as these are likely connected. This operation is fine. As long as you ramp up AVDD before HVDD, the order of powering on AVDD and BVDD should not matter:

    Best regards,

    Samiha