getting readings from the ADS7953

shai kon

Expert 1960 points

Other Parts Discussed in Thread: ADS7953

Hello,

I'm interfacing the ADS7953 with an FPGA master.

According to the datasheet, I understand that the first 16 bit frame after the first CS fall following power up contains invalid data.

Is this correct ?

over 14 years ago

0 Tom Hendrick over 14 years ago

TI__Guru**** 182761 points

Hi Shai,

Your understanding is correct. The first frame of output data from the ADS7953 from power up is not going to contain valid conversion result and the received SDO from the device to your FPGA should be discarded. Assuming you are using all power on default conditions of the ADS7953, the first valid acquisition happens during this frame and the conversion results are then provided on SDO during the second frame.

0 shai kon over 14 years ago in reply to Tom Hendrick

Expert 1960 points

Thanks for the response

As a master, do I have to deassert and reassert the CS line after every 16 bit frame that I send, or I can send the frames back to back without changes in the CS line?

0 Tom Hendrick over 14 years ago in reply to shai kon

TI__Guru**** 182761 points

Hi Shai,

Each new frame starts with a falling edge on the /CS input so yes, as the master you need to assert the /CS input low with each 16-bit write/read to/from the ADS7953.

0 shai kon over 14 years ago in reply to Tom Hendrick

Expert 1960 points

What if I don't pull the CS line high after a 16 bit frame?

Will the device continue to convert and output valid data?

0 shai kon over 14 years ago in reply to Tom Hendrick

Expert 1960 points

0 Tom Hendrick over 14 years ago in reply to shai kon

TI__Guru**** 182761 points

hi shai,

i suspect that the ads7953 will return zeros if the sclk is applied without toggling /cs. take a look at figure 49 and the other flow charts. the /cs needs to toggle to update the mux as well as initialize a new acquisition sequence.

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getting readings from the ADS7953