Failed to encode video buffer

doron sandroy

Intellectual 520 points

Other Parts Discussed in Thread: TVP7002

Hi Larry

I work on DM365/8 card and TVP7002

the componnent input work fine.

i add new res/STD 600/800 rgb from CH 3 i the TVP7002

and add config to the tvp7002.c :

    if (res==600)//600/800 rgb svga
   {
       //TVP7002 set to convert RGB to YCbCr
       err = tvp7002_write_reg(sd,0x01,0x42); //   67); // H-PLL FEEDBACK DIVIDER MSB
       err = tvp7002_write_reg(sd,0x02,0x00); //   20); // H-PLL FEEDBACK DIVIDER LSB
       err = tvp7002_write_reg(sd,0x03,0x58); //   A0); // H-PLL CONTROL
       err = tvp7002_write_reg(sd,0x04,0x80); //   80); // H-PLL PHASE SELECT
       err = tvp7002_write_reg(sd,0x05,0x06); //   32); // CLAMP START
       err = tvp7002_write_reg(sd,0x06,0x10); //   20); // CLAMP WIDTH
       err = tvp7002_write_reg(sd,0x07,0x60); //   60); // HSOUT OUTPUT WIDTH
       err = tvp7002_write_reg(sd,0x08,0x3C); //   00); // BLU FINE GAIN
       err = tvp7002_write_reg(sd,0x09,0x3C); //   00); // GRN FINE GAIN
       err = tvp7002_write_reg(sd,0x0A,0x3C); //   00); // RED FINE GAIN
       err = tvp7002_write_reg(sd,0x0B,0x80); //   80); // BLU FINE OFFSET
       err = tvp7002_write_reg(sd,0x0C,0x80); //   80); // GRN FINE OFFSET
       err = tvp7002_write_reg(sd,0x0D,0x80); //   80); // RED FINE OFFSET
       err = tvp7002_write_reg(sd,0x0E,0x24); //   20); // SYNC CONTROL 1
       err = tvp7002_write_reg(sd,0x0F,0x2E); //   2E); // H-PLL AND CLAMP CONTROL
       err = tvp7002_write_reg(sd,0x10,0x58); //   58); // SYNC ON GREEN THRESHOLD
       err = tvp7002_write_reg(sd,0x11,0x40); //   47); // SYNC SEPERATOR THRESHOLD
       err = tvp7002_write_reg(sd,0x12,0x01); //   01); // H-PLL PRE-COAST
       err = tvp7002_write_reg(sd,0x13,0x00); //   00); // H-PLL POST-COAST
       err = tvp7002_write_reg(sd,0x15,0x43); //   23); // OUTPUT FORMATTER
       err = tvp7002_write_reg(sd,0x16,0x11); //   11); // MISC CONTROL 1
       err = tvp7002_write_reg(sd,0x17,0x00); //   00); // MISC CONTROL 2
       err = tvp7002_write_reg(sd,0x18,0x11); //   11); // MISC CONTROL 3
       err = tvp7002_write_reg(sd,0x19,0xAA); // INPUT MUX SELECT 1
       err = tvp7002_write_reg(sd,0x1A,0x6A); // INPUT MUX SELECT 2
       err = tvp7002_write_reg(sd,0x1B,0x77); //   77); // BLU AND GRN COARSE GAIN
       err = tvp7002_write_reg(sd,0x1C,0x07); //   07); // RED COARSE GAIN
       err = tvp7002_write_reg(sd,0x1D,0x00); //   00); // FINE OFFSET LSB
       err = tvp7002_write_reg(sd,0x1E,0x10); //   10); // BLU COARSE OFFSET
       err = tvp7002_write_reg(sd,0x1F,0x10); //   10); // GRN COARSE OFFSET
       err = tvp7002_write_reg(sd,0x20,0x10); //   10); // RED COARSE OFFSET
       err = tvp7002_write_reg(sd,0x21,0x0D); //   08); // HSOUT OUTPUT START
       err = tvp7002_write_reg(sd,0x22,0x00); //   00); // MISC CONTROL 4
       err = tvp7002_write_reg(sd,0x26,0x80); //   80); // AUTO LEVEL CONTROL ENABLE
       err = tvp7002_write_reg(sd,0x28,0x53); //   53); // AUTO LEVEL CONTROL FILTER
       err = tvp7002_write_reg(sd,0x29,0x08); //   08); // ADC TEST CONTROL
       err = tvp7002_write_reg(sd,0x2A,0x87); //   07); // FINE CLAMP CONTROL
       err = tvp7002_write_reg(sd,0x2B,0x00); //   00); // POWER CONTROL
       err = tvp7002_write_reg(sd,0x2C,0x50); //   53); // ADC SETUP
       err = tvp7002_write_reg(sd,0x2D,0x00); //   00); // COARSE CLAMP CONTROL
       err = tvp7002_write_reg(sd,0x2E,0x80); //   80); // SOG CLAMP CONTROL
       err = tvp7002_write_reg(sd,0x2F,0x0C); //   0C); // RGB COARSE CLAMP CONTROL
       err = tvp7002_write_reg(sd,0x30,0x04); //   04); // SOG COARSE CLAMP CONTROL
       err = tvp7002_write_reg(sd,0x31,0x18); //   18); // AUTO LEVEL CONTROL PLACEMENT
       err = tvp7002_write_reg(sd,0x34,0x03); //   03); // MACROVISION STRIPPER WIDTH
       err = tvp7002_write_reg(sd,0x35,0x00); //   00); // VSYNC ALIGNMENT
       err = tvp7002_write_reg(sd,0x36,0x00); //   00); // SYNC BYPASS
       err = tvp7002_write_reg(sd,0x3D,0x06); //   06); // LINE LENGTH TOLERANCE
       err = tvp7002_write_reg(sd,0x3F,0x00); //   01); // VIDEO BANDWIDTH CONTROL
       err = tvp7002_write_reg(sd,0x40,0xEE); //   47); // AVID START PIXEL LSB
       err = tvp7002_write_reg(sd,0x41,0x00); //   01); // AVID START PIXEL MSB
       err = tvp7002_write_reg(sd,0x42,0x16); //   4B); // AVID STOP PIXEL LSB
       err = tvp7002_write_reg(sd,0x43,0x04); //   06); // AVID STOP PIXEL MSB
       err = tvp7002_write_reg(sd,0x44,0x01); //   05); // VBLK START LINE OFFSET (F0)
       err = tvp7002_write_reg(sd,0x45,0x01); //   05); // VBLK START LINE OFFSET (F1)
       err = tvp7002_write_reg(sd,0x46,0x1C); //   1A); // VBLK DURATION (F0)
       err = tvp7002_write_reg(sd,0x47,0x1C); //   1A); // VBLK DURATION (F1)
       err = tvp7002_write_reg(sd,0x48,0x0); //   00); // F-BIT START LINE OFFSET (F0)
       err = tvp7002_write_reg(sd,0x49,0x0); //   00); // F-BIT START LINE OFFSET (F1)
       err = tvp7002_write_reg(sd,0x4A,0xe3); //   E3); // 1ST CSC COEFFICIENT LSB
       err = tvp7002_write_reg(sd,0x4B,0x16); //   16); // 1ST CSC COEFFICIENT MSB
       err = tvp7002_write_reg(sd,0x4C,0x4f); //   4F); // 2ND CSC COEFFICIENT LSB
       err = tvp7002_write_reg(sd,0x4D,0x2); //   02); // 2ND CSC COEFFICIENT MSB
       err = tvp7002_write_reg(sd,0x4E,0xce); //   CE); // 3RD CSC COEFFICIENT LSB
       err = tvp7002_write_reg(sd,0x4F,0x6); //   06); // 3RD CSC COEFFICIENT MSB
       err = tvp7002_write_reg(sd,0x50,0xab); //   AB); // 4TH CSC COEFFICIENT LSB
       err = tvp7002_write_reg(sd,0x51,0xf3); //   F3); // 4TH CSC COEFFICIENT MSB
       err = tvp7002_write_reg(sd,0x52,0x0); //   00); // 5TH CSC COEFFICIENT LSB
       err = tvp7002_write_reg(sd,0x53,0x10); //   10); // 5TH CSC COEFFICIENT MSB
       err = tvp7002_write_reg(sd,0x54,0x55); //   55); // 6TH CSC COEFFICIENT LSB
       err = tvp7002_write_reg(sd,0x55,0xfc); //   FC); // 6TH CSC COEFFICIENT MSB
       err = tvp7002_write_reg(sd,0x56,0x78); //   78); // 7TH CSC COEFFICIENT LSB
       err = tvp7002_write_reg(sd,0x57,0xf1); //   F1); // 7TH CSC COEFFICIENT MSB
       err = tvp7002_write_reg(sd,0x58,0x88); //   88); // 8TH CSC COEFFICIENT LSB
       err = tvp7002_write_reg(sd,0x59,0xfe); //   FE); // 8TH CSC COEFFICIENT MSB
       err = tvp7002_write_reg(sd,0x5A,0x0); //   00); // 9TH CSC COEFFICIENT LSB
       err = tvp7002_write_reg(sd,0x5B,0x10); //   10); // 9TH CSC COEFFICIENT MSB
   }

i run the demos ,the demo run open the video driver and start get BUF after 3 BUF i get :

envp->videoFile = videoFile.mpeg2
Error: Failed to encode video buffer
ERROR fifoRet == Dmai_EFLUSH

Thanks doron

over 14 years ago

0 Larry Taylor over 14 years ago

TI__Genius 16810 points

Doron,

You are setting up the TVP7002 for 1056 total pixels per line which correlates with the 800x600x60Hz format.

Does this match the VGA input format that you are using? The TVP7002 output clock should be 40MHz for this format.

Try the TVP7002 embedded syncs setup below for 800x600x60Hz. Your settings appeared to be slightly off.

//embedded sync setup
WR_REG,TVP7000,0x01,0x40,0xF2 // AVID Start Pixel LSB - 241 (25 + 216) pixels
WR_REG,TVP7000,0x01,0x41,0x00 // AVID Start Pixel MSB
WR_REG,TVP7000,0x01,0x42,0x16 // AVID Stop Pixel LSB - 1045 (241 + 800 + 4) pixels
WR_REG,TVP7000,0x01,0x43,0x04 // AVID Stop Pixel MSB
WR_REG,TVP7000,0x01,0x44,0x01 // VBLK F0 Start Line Offset - 1 line
WR_REG,TVP7000,0x01,0x45,0x01 // VBLK F1 Start Line Offset
WR_REG,TVP7000,0x01,0x46,0x1C // VBLK F0 Duration - 28 lines
WR_REG,TVP7000,0x01,0x47,0x1C // VBLK F1 Duration

Are you configuring the DM part for 800x600 active frame capture?

0 doron sandroy over 14 years ago in reply to Larry Taylor

Intellectual 520 points

Hi Larry thanks to the answer .

i get from TI this :http://e2e.ti.com/support/data_converters/videoconverters/f/376/t/155614.aspx#563848

Ther is a difference from the register seting .

i try the 2 seting and i get the same stack .

Thanks doron.

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Failed to encode video buffer