Other Parts Discussed in Thread: ADS1282
Tool/software:
Hello,
In order to properly interrupt an acquisition sequence in the FPGA controlling the ADC, we are interested in knowing the behaviour of the ADS1282-SP when receiving an SDATAC command right after having received an RDATA command ?
Will the ADC ignore the SDATAC command and output a falling edge on DRDY once new data is ready ? Or will the SDATAC command have for effect to suppress the DRDY output even if the ADC was in RDATA mode and not RDATAC ?
Thank you.
Regards,
Périg (Electronics engineer)