Tool/software:
I want to connect two different FPGAs to the two channels of ADC12DJ5200RF. Is this approach feasible? How should the circuit be designed for the clock and synchronization?
Tool/software:
I want to connect two different FPGAs to the two channels of ADC12DJ5200RF. Is this approach feasible? How should the circuit be designed for the clock and synchronization?
Hello,
The ADC can interface with two different FPGAs in 64b66b modes of operation. It also must be noted that in single channel modes of operation the data will be split across both lanes and must be interleaved to create the final data rate stream, so this will need to be taken care of. For synchronization you must route both SYSREF and CLK from phase synchronous sources.
Thanks,
Eric