Other Parts Discussed in Thread: TSW12QJ1600EVM
Tool/software:
Hi,
I cannot seem to get the QPLL to lock in a design I am working on. I am using a TSW12QJ1600EVM connected to a Xilinx VCU118 dev bd. I have mapped the correct pinouts, have verified that I am getting a ref clk, and think that I have it set up correctly, but it will not lock. I have tried, QPLL0, QPLL1 and CPLL but nothing will lock. Here are the GT xcvr setting and the ADC GUI I am using. Is there a reset sequence I am missing?
