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ADS8686S: Serial communication not working

Rui Coutinho
Prodigy 20 points

Part Number: ADS8686S

Tool/software:

Hi, I'm trying to make my own DSP (Digital Signal Processor) board, and I'm using the ADS8686S. I followed the power recommendations and layout example on the datasheet (pages 106-107). The following image has the connections I made on the PCB. I tried using 1 MHz, 500 kHz and 100 kHz of clock frequency, for the SPI communication. I intended to use the software mode.

 ADS8686S connections 

I tried to read the register CONFIGURATION (ADDR: 0x02). The following image is the logic analyser print of the signals at 100 kHz of clock frequency, for the other frequencies tested, the response was identical.

logic_analyser

One thing that I don't understand in the image above is when I'm sending the address, the bits change on the falling edge to be read on the rising edge. However, when the ADC sends the data, it changes the values on the rising edge. That makes the logic analyser show the values above, however my microcontroller (MCU) always reads 0x00FF. The datasheet says the reset value of this register is 0x0400.

In my code, I do a full reset of 20us and wait 30ms. After that, I start the communication. I wait 2us between putting CS to low and start the transmission.

Can anyone tell me what I'm doing wrong? 

I already measured the voltage on the power pins and all the pins have the expected voltage. I'm using the SPI with no phase (CPHA=0) and no polarity (CPOL=0), however I already tried all the combinations possible and this configuration was the only one that got an answer from the ADC.

  • 0
    TI__Expert 7510 points

    Hello Rui, 

    Welcome to TI's E2E forum! 

    Thank you for all of the information shared, the device configuration (pinout shared) looks good and seems to match the configuration explained. 

    I think what is happening in the logic image shared is that the data is shifted, the device appears to be registering a command to read register 0x4 (0x0800) instead of register 0x2 (0x0400). The data output in the following frame matches register 0x4 since it seems to output 0x00FF.  The format for the register data readout is D[15:8] = 0x00,D[7:0] = Register data.   

    Reading from ADC (SCLK & SDOx):

    • After CS goes low, it takes t0_CKDO (<16 ns, DVDD-dependent) for valid data on SDOx.
    • Data must be valid at least 3 ns before an SCLK rising edge.
    • Once valid, data holds for tD_CKDO (~20 ns) after the rising edge before changing.
    • This repeats for 16 clocks. On the last rising edge, SDOx returns to Hi-Z within 20 ns.

    Implication: Data changes on the rising edge of SCLK, so the controller should sample on the falling edge to avoid missing data.

    Writing to ADC (SCLK & SDI):

    • The ADC latches SDI on the falling edge of SCLK.
    • Timing requires:
      • tSU_DINCK ≥10 ns before the falling edge (setup)
      • tH_CKDIN ≥8 ns after the falling edge (hold)

    Therefore, SDI should change on the rising edge so it is stable across the falling edge.

    Recommended SPI Modes: CPOL=0, CPHA=1 or CPOL=1, CPHA=0

    You mentioned using CPOL=0, CPHA=0, which has the two following risks:

    1. Delay from CS low → 1st SCLK rising edge can cause SDO data to shift by one bit if the controller isn’t fast enough.
    2. For SDI, if data changes too close to the falling edge, the ADC may latch unstable data, also causing a bit shift.

    In your case since you mentioned your controller is reading 0x00FF it might be that its fast enough to possibly read the SDO data correctly, but in turn it might be too fast to where the ADC might be latching the data on the SDI early. 

    You mentioned trying all of the SPI modes, was this just with the logic analyzer or was this with the controller as well?

    Best regards, 

    Yolanda

  • 0 in reply to Yolanda Gonzalez
    Prodigy 20 points

    Hi,

    Thank you so much for your timely response.

    I tested the modes you suggested, and the issue is fixed. My problem was that I was expecting the reading to have the bits of the register and not have the 8 MSB always at 0. For example, the datasheet says the reset value of address 0x2 is 0x400, so I was expecting to read 0x400 after the reset. I would propose to make more evident the fact the 8 MSB are always zero when reading.

    One thing I noticed is that the communication needs to have CPOL=1, CPHA=0. Otherwise, I was having a bit shift.

    Below are the images of the logic analyser, reading a register, then write to that register a different value and after that, read again to confirm the write command. The MCU also reads the same values.

    Thanks so much for the help!!!