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A possible ADS1298 SPI port problem

Xiang Liu92822
Prodigy 40 points
Other Parts Discussed in Thread: ADS1298

Hi everyone,

In our design, we use FPGA, in stead of the DSP, to control the ADS1298 dev front-end.  

The problem now is that  ADS1298 doesn't response to the conversion start command sent through the SPI port(the /DRDY pin keeps high all the time after we sent this command).

If using the other way to start the conversion: set the START pin to be '1',  the /DRDY pin would be pulled down every 4ms, which is the default setting in the chip,  but if we put a 5M Hz clock signal on the SCLK pin to retrieve data,  the DOUT pin is always high(the /DRDY signal does jump back to high after the first SCLK clock period). 

We have verified that /CS, /PWDN, /RESET are set to high; CLKSEL is also set to high to use the internal clock. And we  verified that the AVDD, AVSS and DVDD are powers up properly.

We wonder if you could help us to figure out what could be the problem or what we might do next for debugging.

Thanks in advance!

Xiang 

  • 0
    TI__Guru**** 174800 points

    Hi Xiang,

    Take a look over the Frequently Asked Questions for the ADS1298, you may find some helpful detail there.  The link for the page is here:

    http://e2e.ti.com/support/data_converters/precision_data_converters/w/design_notes/frequently-asked-ads1298-and-ads1198-questions.aspx

    When you say you verify that /CS is high - is your FPGA toggling that pin while you send your SPI commands?  The first debug steps you should consider are writing to and reading from different registers in the ADS1298.  Try changing the CONFIG registers to something other than their default values and verify that you can read back the same data that you wrote.

  • 0 in reply to Tom Hendrick
    Prodigy 40 points

    Hi Tom,

    Sorry that The /CS is actually always low. The /CS pin on ADS1298 is connected  with a FPGA output pin, which is always assigned to '0'. I will implement the register read back function and try it as soon as possible. Thanks for the suggestion.

    Regards,

    Xiang

  • 0 in reply to Tom Hendrick
    Prodigy 40 points

    Hi  Tom,

    We tried to read back the device setting register(with the address "00h") value, but it seems there is no real data on DOUT(it's always '0').  Following are some  pictures about the signal we got:

    The first picture shows the SPI port signal captured in FPGA by SignalTap II.

         Picture 1: ADC_CS, ADC_DOU, ADC_DIN, and ADC_SCLK are the corresponding SPI signals

    The second picture shows the same SPI port signal captured on the ADS1298 pins through oscilloscope.

                   Picture 2: Channel 1 is SCLK, channel 2 is DOUT

    The third one shows some detail about the signal in picture 2.

                                Picture 3: Channel 1 is SCLK, channel 2 is DOUT

     By pulling the START pin up to '1' and then monitoring the /DRDY pin, we verified that the ADS1298 was actually working.  So we wonder if it's possible that the SPI port has been locked for some reason.

    Thanks,

    Xiang

  • 0 in reply to Xiang Liu92822
    TI__Guru**** 174800 points

    Hi Xiang,

    If the SPI transfer gets corrupted for some reason, the easiest way to reset the serial communication to the ADS1298 is to toggle the /CS input.  Try using an active /CS and be sure to send it low before writing your config registers and then high after the transfer is complete.  If you power up the ADS1298 into its default state and see the DRDY signal pulsing, then you should be able to read back the default configuration register values.  Check the wiring between the EVM and your FPGA setup and make sure you have good connections between the boards.