Tool/software:
I'm experiencing strange behavior with the LM98714 component.
I'm using the following modes:
1) sample & hold
2) CMOS output
3) external VCLP
4) Slave Timing Generator Mode
5) 3 Channel Mode.
6) Input Polarity to 1
7) ADCCLK User supplies ADC rate clock: Main Configuration 1 bit 2 to 0
I'm noticing some strange behavior:
If I change the Color Black Level registers, which represent a Binary Format offset number, I always get a subtraction of the offset from 0 to 1023. Is this working correctly?
If I change Main Configuration 2, Gain Mode Select bit 4, I don't notice a doubling of the signal dynamic range, but only when the input signal is high.
If I increase the PGA to increase the signal dynamic range, if some pixels saturate, I get a ghost effect in adjacent channels,
how I can't mitigate.
The ADC frequency is set to 24 MHz with an 8 MHz pixel clock.
It seems that the clamp phase where it acquires the external VCLP isn't working properly.