Tool/software:
Hello E2E Support Team,
The AFE58JD48 datasheet has multiple tables and diagrams related to latency in JESD mode, but I'm struggling to find similar information when using LVDS. The parameter "NLAT" is shown in Figures 135-137, but doesn't appear to be defined anywhere in the document. Can you please provide the basic ADC latency as well as any additional cycles for digital processing, down-conversion, and decimation.
I appreciate your assistance.
Steve Claffey