Other Parts Discussed in Thread: MSP430FR5969
Tool/software:
Hi,
I am using MSP430FR5969 to set DACs and read ADCs from v62/22614-01xe (AFE11612PAPSEP). The AFE11612 is controlled over SPI bus (2 MHz clock) as a standalone device. When I read the ADCs consecutively I get zeros but if I put a delay at the end of each 3 byte SPI transaction I get data. The following is my setup for the AFE:
/* AFE configuration commands */
/*ADC internal ref, CMODE manual */
const uint8_t AFE_AMC_0[] = {0x4C, 0x34, 0x00};
/*False alarm protection bits */
const uint8_t AFE_AMC_1[] = {0x4D, 0x03, 0x70};
/*DAC config - Channels asynchronous out */
const uint8_t AFE_CONF_REG[] = {0x58, 0x00, 0x00}; // update DAC immediately
/* Enable ADC channels 0 - 6, 8-9 and 12 */
const uint8_t AFE_ADC_EN[] = {0x50, 0x6D, 0xD9};
const uint8_t AFE_PWR_DN[] = {0x6B, 0x7F, 0x90};
The delay, I arbitrarily chose, was 62.5 usec (using the __delay_cycles(1000) function and the MSP is running at 16 MHz). I read through the datasheet to see if there was some literature on timing but did not find anything that pointed to this issue. Maybe there is an issue with my setup or the afe requires a delta T between reads. Can you please help ?
Thanks
Atma