ADC3543: Using single ended clock. Trouble getting part configured and data output

Hi Simon,

If the ADC device was working before, what has changed?

If the ADC is of suspect, then I would replace it and see if you can get your board working again.

Regards,

Rob

I think when it momentarily worked there was a few bad solder joints that may have gotten "fixed" with flux residue. I have since reflowed the board and confirmed the joints are good with a microscope. I wouldn't read into it momentarily working - I could have hallucinated it from spending too much time in the lab (joking of course but I think we should focus on the problem at hand). 

The symptoms are as described above (but the bad solder joint was on the VREF pin so that is fixed). The chip appears to show signs of life:

When configuring the VREF over SPI it shows up on the VREF pin and when configuring the clock to be single ended it disconnects the 0.9Vcm bias from the unused clock pin. In addition to SPI reading back correctly this to me screams that everything is working as expected. However there is still no data output.

Is it possible that I am doing something sufficiently incorrect in the register settings? Can you provide what register writes I need to do for a minimal viable CMOS parallel SDR output, internal reference, single ended clock (default bit mapping, no down-converting/filtering/mixing)

Best,

Simon

Hi Simon,

It might be easier for you to send us your reg config first and I can test in the lab.

Please also send sampling rate, I assume you are using 2 wire for the digital config?

And just to confirm, you are using a single ended input clock config?

One thought, what are you using to drive the sampling clock on your board?

Regardless, I see it is not DC blocked, I would put a series 0.1uF cap inline with your clock connection.

The clock swing could be good, but the common mode voltage might be off.

Try that too and let me know.

Thanks,

Rob

Hi Rob, Thank you for your prompt replies.

As you can see in the screenshot of the scope. I am using a 50MHz single ended clock to drive the sampling rate. I am indeed using the SPI config and I am setting registers successfully. register reads appear correct. I can attach a scope trace of the SPI transaction if you would like but I am fairly confident that the two wire config interface is working correctly

I have attempted setting register 0x0E to value 0b00001001, that is REF CTL set to 1, REF SEL set to 00 for internal reference, and SE CLK EN 1 for single ended clock. I can attach the C "psudo" code for my initialization.

I am driving the clock with a CDCV304 and a voltage divider to bring it down to 1.8 logic level. See original post for a scope trace of the clock probed near the ADC. Putting a series 0.1uF is an interesting idea, although the datasheet explicitly shows the direct connection in section 8.3.2.1. 

I am attaching the initialization code.

void video_adc_init()
{
    sleep_ms(100); // wait for the ADC to power up
    // clock idle low -> CPOL_0
    // data sampled on rising edge -> CPHA_0
    // MSB first -> MSB_FIRST
    // 8 bits per word -> 8
    spi_set_format(LOCAL_SPI_PERIPHERAL, 8, SPI_CPOL_0, SPI_CPHA_0, SPI_MSB_FIRST);

    // starting with a reset is prudent
    //  write a 1 to bit 0 of register 0x00 to reset the ADC
    write_video_adc(0x00, 0b00000001); // reset the ADC
    sleep_ms(1);

    // Register 0x07 has bits 7-5 OP IF MAPPER need to be set to 110 for SDR
    // bit 4 must be set to 0
    // bit 3 is OP IF EN (enables changing the default interface mode ) write 1
    // bit 2-0 are OP IF SEN select output interface set 000 for SDR CMOS
    write_video_adc(0x07, 0b11001000);
    sleep_us(10);


    // now load config from efuses
    // register 0x13 bit 0 set 1
    write_video_adc(0x13, 0b00000001); // set to load config from efuses
    sleep_ms(2);                       // wait for the ADC to load the config from efuses
    write_video_adc(0x13, 0b00000000); // clear the load config bit
    sleep_us(10);

    // write power down stuff for SDR CMOS
    write_video_adc(0x0A, 0x60);
    sleep_us(10);
    write_video_adc(0x0B, 0x1E);
    sleep_us(10);
    write_video_adc(0x0C, 0x0C);
    sleep_us(10);

    //power down DCLKIN
    write_video_adc(0x18, 0x00);
    sleep_us(10);

    //note that flow chart wants 0x19 to be written to possibly
    //contains FCLK config (used in decimation)

    //setup the bit mapper to be off...
    write_video_adc(0x1B, 0x00);
    sleep_us(10);

    //enable DCLK
    write_video_adc(0x1F, 0b00010000);
    sleep_us(10);

    //this is where one might adjust soemthing about FCLK and duty cycle in 0x20..2

    //now one might adjust the bitmaper in 0x39..72

    //disable the DDC and enable bypass
    write_video_adc(0x24, 0x00);
    sleep_us(10);

    //we can now configure the decimation in 0x25

    //can program NCO here in 0x2A..D

    //configure complex stuff in 0x27

    // set mixer gain in 0x26

    //The flowchart in the datasheet ends here. Looking at the remaining registers that have not yet been adjusted...

    //power down controls
    //bit 5 turns off clock buffer can make power come back
    write_video_adc(0x08, 0b00000010);
    sleep_us(10);
    //0x0D does power down mask (what the power down pin turns off) ignored

    //setup the voltage reference and clock mod 0x0E
    // bit 7-5 control sync (we dont really care about this)
    // bit 4 must be 0
    // bit 3 write 1 to set ref and clk using spi
    // bit 2-1 ref sel write 00 for internal ref
    // bit 0 write 1 for single ended clock
    write_video_adc(0x0E, 0b00001001); // set to internal ref and single ended clock
    sleep_us(10);

    // configure the ADC input, set differential and DLL PDN
    write_video_adc(0x11, 0x00);
    sleep_us(10);

    //turn off test pattern
    write_video_adc(0x14, 0x00);
    sleep_us(10);
    write_video_adc(0x15, 0x00);
    sleep_us(10);
    write_video_adc(0x16, 0x00);
    sleep_us(10);

    //set the DCLK output delay
    write_video_adc(0x1E, 0x00);

    sleep_us(100);

    // This function reads all the registers one by one and I have scoped them and confirmed that have all taken the expected values.
    read_all();

}

As a higher level question. Do I need to do any configuration to see signs of life from this chip? Should it not just output data as soon as a clock is seen on the input regardless of what configuration I put in? What can cause my symptoms of no data but SPI signs of life?

HI Simon,

Please answer my questions above about the clock and provide the register writes performed.

Yes, the ADC should show signs of life when the power is brought up.

Which leads me to think you have a bad ADC if you had shorted leads and powered the device on as mentioned at the start.

It would be best to start with a fresh ADC or board. 

Regards,

Rob

Thank you Rob,

Yes I am starting to suspect the chip. I guess I have done enough due diligence to justify swapping it now. I have one on order and will update when it arrives.

As I said above:

• The sampling rate is 50MHz.
• I am using 2 wire config with 100kBit/s data rate.
• I am using single ended clock config. 
• Clock is driven by CDCV304 and a voltage divider to bring it down to 1.8 logic level

I attempted your suggestion of AC coupling the clock but sadly it did not help my issue. 

While I wait for the new parts to arrive can you look at my register configs...

wait 100ms
0x00, 0b00000001
wait 1ms
0x07, 0b11001000
0x13, 0b00000001
wait 2ms
0x13, 0b00000000
0x0A, 0x60
0x0B, 0x1E
0x0C, 0x0C
0x18, 0x00
0x1B, 0x00
0x1F, 0b00010000
0x24, 0x00
0x08, 0b00000010
0x0E, 0b00001001
0x11, 0x00
0x14, 0x00
0x15, 0x00
0x16, 0x00
0x1E, 0x00
wait 100us

Thank you,

Simon

Hi Simon,

So you put a 0.1uF series DC blocking cap between the CDC device and the ADC?

Can you measure the common mode DC voltage on the clock pin you are driving? It should be around 0.9VDC.

Might be good to draw out for me what is actually being connect as a clock to the ADC, basically on what was done and what you are doing now?

If you put too big a signal swing into the ADC clock pin, you likely destroyed that input, and would never get a clock into the ADC.

And therefore, never get any digital outputs to toggle.

Thanks,

Rob

Hi Rob,

Indeed. I put a 0.1uF capacitor blocking DC between the CDC device and the ADC. The common mode DC voltage is around 0.9V as expected.

I replaced the ADC chip and it sprung into life. I must have had a dud, or accidentally hurt it at some point.... Thank you for your input it was very helpful.

I have yet to try removing the capacitor and running the chip in single ended clock mode. Is there any reason why running with a single ended clock AC coupled into the chip would be bad? Effectively the common mode voltage of the clock is now being jerked around along with the clock.

Will this alias to DC and degrade the ADC performance? As of now I appear to be seeing slightly more noise than advertised. (My application cares more about DC-fewMHz performance rather than pure spectral performance in the MHz).

Best,

Simon

Hi Simon,

Its better to run the clock differential. From the schematic above it is being driving single-ended.

If you are having noise issues, you need to first improve the clock performance, ie - lower phase noise/jitter, on the sampling clock.

What is being used to clock the ADC, before the CDC device?

Regards,

Rob