ADS127L18EVM-PDK: ADS127L18 or ADS127L14 - Question about 2:1 or 4:1 channel averaging

Part Number: ADS127L18EVM-PDK
Other Parts Discussed in Thread: ADS127L14, ADS127L11, ADS127L18, THS4551, THP210

Tool/software:

Hi, I am interested in lowest possible noise while maintaining sampling rate 50ksps or above. And for that I see the sweetspot is for my case sinc4 filter at OSR24 or 32, where at Fclk 25.6 or 32.768 MHz, the en noise is in 8.05 - 10.4uVrms range. I am referring here to the  Table 6-2 of datasheet. I was checking the datasheet of another ADC AD4134  where I found interesting informationa about 2:1 / 4:1 channel averaging: 

"The AD4134 is also capable of performing on-board averaging between two or four of its input channels. The result is a near 3 dB, if two channels are combined, or 6 dB, if all four channels
are combined, improvement in dynamic range while maintaining the bandwidth."

The relevant data for these settings are give in AD4134 datasheet table 13 and indeed the rms noise for 4:1 ch aveaging falls down to 4.66 uV.

ADS127L14/18 datasheet p. 63 also mentions that averaging, but no specs nor much details are given. Can you please help clarify this if, ADS127L14/18 , will give the same noise advantage of 6dB when doing 4:1 ch. averaging? And will it also maintaining the bandwidth? Are there other considerations when one tries to do channel averaging, particularty with sinc4 and OSR24/32 in the sweetspot I mentioned? Basically I want to use the ADC as single channel, at 500ksps but to get even lower uncorrelated noise (post-filter) than it has for sinc4 filter, while maintaining other specs.

By the way I am familiar with ADS127L11 - single channel version, I use its evaluation board and quite happy with performance. 

Thanks in advance!

Karen

  • I had a typo - I meant 500ksps, not 50, and if that helps my signal is normally below 80kHz so the -3dB 116 to 155 kHz in Table 7-3 suit me well. Also I wanted to make sure we are talking her about inside-ADC averaging, not later-in-FPGA averaging.

  • Hello Karen,

    Yes, the ADS127L14/18 supports internal channel averaging.  You could also do this externally in an FPGA, but having this feature built inside of the ADC reduces the amount of data transfer to the FPGA, which can reduce IO count and reduce power consumption.

    Yes, the ADS127L14/18 will provide a noise advantage of 6dB, or reduction of noise by 1/2, when using 4:1 channel averaging.  If you have an ADS127L18EVM, you can confirm this on the EVM as well.  If using the ADS127L18, you can also configure for 8:1 channel averaging, resulting in a noise floor of 8.05uVrms/sqrt(8)=2.85uVrms when using the SINC4 filter with OSR32..

    Channel averaging does not effect bandwidth.  However, if you adjust the CLK frequency to obtain a specific data rate.  For example, using max-speed, SINC4 with OSR32, and Fclk=32MHz will result in a sample rate of exactly 500ksps.  The f-3db will also be reduced proportionally from 116.3kHz with f-CLK=32.768MHz down to f-3dB=32/32.768*116.3=113.6kHz with f-CLK=32MHz.

    From a system perspective, as long as you enable the input buffers on each of the channels, you should be able to directly connect all channel inputs together and drive from a single input amplifier such as the THS4551 or THP210.

    Regards,
    Keith Nicholas
    Precision ADC Applications

  • Hi Keith,

    Thanks for thorough information. Basically as you confirmed there is no penalty in doing 4:1 or 8:1 averaging, except of course the cost increase and more complex layout. By the way  a, a buffer amplifier I intend to use in any case, and considering my signal won't exceed 150kHz, the  THP210 sems like a great choice.