Tool/software:
Hi,
my customer wants to use an external clock, but is not sure which logic level height is needed for the clock-signal.
Can you provide further requirements for the clock signal (frequency stability, jitter e.g.)?
Thanks
Hello Franziskus,
The clock input is referred to the DVDD supply and should be a standard CMOS level.
The clock frequency can be in the range of 0.1MHz up to 16MHz, and needs a duty cycle from 40% to 60%.
There is really no requirement on clock 'stability', but the output data rate will be directly proportional to the clock frequency, so this should be considered.
Clock jitter can increase the noise when measuring AC signals, and depends on the input signal frequency and the amount of over-sampling inside the ADC. The basic equation for jitter related SNR is:
Where the SNRupperLimit should be 10dB greater than the ADC's SNR for a specific data rate. OSR is the over-sampling ratio. The ADS1258 datasheet does not directly specify this value, so I have provided it below.
| DRATE[1:0] | Input Noise (uVrms) | SNR (dB) | OSR |
| 11 | 12 | 107.7 | 64 |
| 10 | 7.9 | 111.3 | 256 |
| 01 | 4.5 | 116.2 | 1024 |
| 00 | 2.8 | 120.3 | 4096 |
For example, on the DRATE range of 11 (125000sps when f-CLK=16MHz), assume you want to measure an input signal with frequency f-in=10kHz. The approximate SNR of the ADC in this configuration is approximately 107.7dB, so setting the SNR upper limit to 117.7dB, and solving for t-jitter:
117.7 = -20*log(2*PI*10000*t-jitter) +10*log(64); solving for t-jitter
t-jitter = 166ps-rms, just about any commercially available oscillator can meet this requirement.
If you only want to measure DC signals, where the bandwidth is typically assumed to be in the 0.1Hz to 10hz range, the resulting t-jitter = 166ns-rms. Any simple RC oscillator can typically meet this requirement.
Please refer to this TI Precision Lab video for more details:
https://www.ti.com/video/6360889031112
Regards,
Keith Nicholas
Precision ADC Applications
